From a68ffdd6c327bcc5d0c0524c4dacd6ceeaf839d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Sat, 31 Jan 2015 09:03:06 +0100 Subject: Adding all main hw source files and constraints. --- rtl/src/ipcore/_xmsgs/cg.xmsgs | 27 +++++++++++++++++++++++++++ rtl/src/ipcore/_xmsgs/pn_parser.xmsgs | 15 +++++++++++++++ 2 files changed, 42 insertions(+) create mode 100644 rtl/src/ipcore/_xmsgs/cg.xmsgs create mode 100644 rtl/src/ipcore/_xmsgs/pn_parser.xmsgs (limited to 'rtl/src/ipcore/_xmsgs') diff --git a/rtl/src/ipcore/_xmsgs/cg.xmsgs b/rtl/src/ipcore/_xmsgs/cg.xmsgs new file mode 100644 index 0000000..985e6e3 --- /dev/null +++ b/rtl/src/ipcore/_xmsgs/cg.xmsgs @@ -0,0 +1,27 @@ + + + +Generating IP... + + +A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten. + + +A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten. + + +Component clk_wiz_v3_6 does not have a valid model name for Verilog synthesis + + +Finished generation of ASY schematic symbol. + + +Finished FLIST file generation. + + + + diff --git a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..2ccce38 --- /dev/null +++ b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ + + + + + + + + + + +Analyzing Verilog file "E:/__DNSSEC/novena_baseline/src/ipcore/clkmgr_dcm.v" into library work + + + + -- cgit v1.2.3