From a68ffdd6c327bcc5d0c0524c4dacd6ceeaf839d7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Sat, 31 Jan 2015 09:03:06 +0100
Subject: Adding all main hw source files and constraints.

---
 rtl/src/ipcore/_xmsgs/pn_parser.xmsgs | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 rtl/src/ipcore/_xmsgs/pn_parser.xmsgs

(limited to 'rtl/src/ipcore/_xmsgs/pn_parser.xmsgs')

diff --git a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
new file mode 100644
index 0000000..2ccce38
--- /dev/null
+++ b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/__DNSSEC/novena_baseline/src/ipcore/clkmgr_dcm.v&quot; into library work</arg>
+</msg>
+
+</messages>
+
-- 
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