From 13b8166c8989b5e83b0c998279c60c17bf46e890 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Thu, 5 Feb 2015 15:31:33 -0500 Subject: add all SHA cores (hello coretest_hashes) --- rtl/build/Makefile | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 rtl/build/Makefile (limited to 'rtl/build/Makefile') diff --git a/rtl/build/Makefile b/rtl/build/Makefile new file mode 100644 index 0000000..ec03197 --- /dev/null +++ b/rtl/build/Makefile @@ -0,0 +1,32 @@ +project = novena_baseline_top +vendor = xilinx +family = spartan6 +part = xc6slx45csg324-3 +top_module = novena_baseline_top +isedir = /opt/Xilinx/14.7/ISE_DS +xil_env = . $(isedir)/settings64.sh + +vfiles = \ + ../src/verilog/novena_baseline_top.v \ + ../src/verilog/novena_clkmgr.v \ + ../src/verilog/cdc_bus_pulse.v \ + ../src/verilog/eim_arbiter.v \ + ../src/verilog/eim_da_phy.v \ + ../src/verilog/eim_arbiter_cdc.v \ + ../src/verilog/core_selector.v \ + ../src/verilog/eim_indicator.v \ + ../src/ipcore/clkmgr_dcm.v \ + ../../../../core/sha256/src/rtl/sha256_core.v \ + ../../../../core/sha256/src/rtl/sha256_k_constants.v \ + ../../../../core/sha256/src/rtl/sha256.v \ + ../../../../core/sha256/src/rtl/sha256_w_mem.v \ + ../../../../core/sha1/src/rtl/sha1_core.v \ + ../../../../core/sha1/src/rtl/sha1.v \ + ../../../../core/sha1/src/rtl/sha1_w_mem.v \ + ../../../../core/sha512/src/rtl/sha512_core.v \ + ../../../../core/sha512/src/rtl/sha512_h_constants.v \ + ../../../../core/sha512/src/rtl/sha512_k_constants.v \ + ../../../../core/sha512/src/rtl/sha512.v \ + ../../../../core/sha512/src/rtl/sha512_w_mem.v + +include xilinx.mk -- cgit v1.2.3 From 0e4e0b5d71b15e1f4edf31295fc95d45d4ae3890 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 10 Feb 2015 13:51:40 -0500 Subject: First stage of integration cleanup. Add local SHA core wrappers, due to the need for registered outputs. Remove unused demo-adder code, and reorganize sw directory. --- rtl/build/Makefile | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) (limited to 'rtl/build/Makefile') diff --git a/rtl/build/Makefile b/rtl/build/Makefile index ec03197..cfac6ae 100644 --- a/rtl/build/Makefile +++ b/rtl/build/Makefile @@ -7,26 +7,30 @@ isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings64.sh vfiles = \ - ../src/verilog/novena_baseline_top.v \ - ../src/verilog/novena_clkmgr.v \ ../src/verilog/cdc_bus_pulse.v \ + ../src/verilog/cipher_selector.v \ + ../src/verilog/core_selector.v \ + ../src/verilog/eim_arbiter_cdc.v \ ../src/verilog/eim_arbiter.v \ ../src/verilog/eim_da_phy.v \ - ../src/verilog/eim_arbiter_cdc.v \ - ../src/verilog/core_selector.v \ ../src/verilog/eim_indicator.v \ + ../src/verilog/eim_memory.v \ + ../src/verilog/novena_baseline_top.v \ + ../src/verilog/novena_clkmgr.v \ + ../src/verilog/novena_regs.v \ + ../src/verilog/rng_selector.v \ + ../src/verilog/sha1.v \ + ../src/verilog/sha256.v \ + ../src/verilog/sha512.v \ ../src/ipcore/clkmgr_dcm.v \ + ../../../../core/sha1/src/rtl/sha1_core.v \ + ../../../../core/sha1/src/rtl/sha1_w_mem.v \ ../../../../core/sha256/src/rtl/sha256_core.v \ ../../../../core/sha256/src/rtl/sha256_k_constants.v \ - ../../../../core/sha256/src/rtl/sha256.v \ ../../../../core/sha256/src/rtl/sha256_w_mem.v \ - ../../../../core/sha1/src/rtl/sha1_core.v \ - ../../../../core/sha1/src/rtl/sha1.v \ - ../../../../core/sha1/src/rtl/sha1_w_mem.v \ ../../../../core/sha512/src/rtl/sha512_core.v \ ../../../../core/sha512/src/rtl/sha512_h_constants.v \ ../../../../core/sha512/src/rtl/sha512_k_constants.v \ - ../../../../core/sha512/src/rtl/sha512.v \ ../../../../core/sha512/src/rtl/sha512_w_mem.v include xilinx.mk -- cgit v1.2.3