From 86ec8c4b2d539814d3102061f099c77e574fc743 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Sun, 1 Feb 2015 20:05:36 +0100 Subject: Updated README with more info about the base. --- README.md | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index 11aff35..8ffaa78 100644 --- a/README.md +++ b/README.md @@ -1,8 +1,23 @@ -Novena base ------------ -This repo contains the Novena baseline developed as part of the Cryptech -project. The design contains a new FPGA top level, now clock -implemetation and reworked EIM interface. +# Cryptech Novena FPGA baseline # + +## Introduction ## + +This repo contains the Novena FPGA baseline developed as part of the +Cryptech project. The design contains a new FPGA top level, now clock +implementation and reworked EIM interface. + +The main purpose of the baseline is to allow us to run the Cryptech +cores and FPGA system with the general system clock and then interface +to the EIM with the EIM burst clock. + + +## Technical details ## + +The design tries to be a clean top that is easy for others to work on +and adapt to their needs. The top is stripped from ports not needed for +the baseline. All clock and reset implementation is placed in a separate +module. The EIM interface is in a separate module and then the rest of +the system is in a third module. Internally the baseline contains an arbiter to connect cores with a 32-bit memory like interface to the EIM. Finally there is SW to @@ -12,4 +27,7 @@ FPGA. For information about the EIM clocking and the baseline HW and SW design, see the documentation. + +## Author ## + The baseline has been written by Pavel Shatov. -- cgit v1.2.3