From 01669dcd3d341e43e1f1a03f837d3d5aac880009 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Wed, 4 Feb 2015 13:58:27 -0500 Subject: change 'unsigned int' to the more explicit 'uint32_t' --- sw/test-sha256/novena-eim.c | 143 ++++++++++++++-------------- sw/test-sha256/novena-eim.h | 224 ++++++++++++++++++++++---------------------- 2 files changed, 184 insertions(+), 183 deletions(-) diff --git a/sw/test-sha256/novena-eim.c b/sw/test-sha256/novena-eim.c index 9ea76ef..1effff1 100644 --- a/sw/test-sha256/novena-eim.c +++ b/sw/test-sha256/novena-eim.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include "novena-eim.h" @@ -38,7 +39,7 @@ int eim_setup() // determine memory page size to use in mmap() mem_page_size = sysconf(_SC_PAGESIZE); if (mem_page_size < 1) - { printf("ERROR: sysconf(_SC_PAGESIZE) == %l\n", mem_page_size); + { printf("ERROR: sysconf(_SC_PAGESIZE) == %ld\n", mem_page_size); return -1; } @@ -117,52 +118,52 @@ void _eim_setup_iomuxc() reg_pad.reserved_31_17 = 0; // must be 0 // all the pins must be configured to use the same ALT0 mode - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_RW, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD00, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD01, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD02, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD03, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD04, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD05, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD06, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD07, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD08, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD09, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD10, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD11, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD12, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD13, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD14, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD15, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B, (unsigned int *)®_mux); - eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK, (unsigned int *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_RW, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD00, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD01, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD02, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD03, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD04, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD05, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD06, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD07, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD08, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD09, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD10, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD11, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD12, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD13, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD14, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_AD15, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B, (uint32_t *)®_mux); + eim_write_32(IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK, (uint32_t *)®_mux); // we need to configure all the I/O pads too - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_RW, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD00, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD01, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD02, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD03, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD04, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD05, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD06, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD07, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD08, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD09, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD10, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD11, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD12, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD13, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD14, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD15, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B, (unsigned int *)®_pad); - eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK, (unsigned int *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_RW, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD00, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD01, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD02, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD03, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD04, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD05, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD06, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD07, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD08, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD09, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD10, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD11, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD12, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD13, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD14, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_AD15, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B, (uint32_t *)®_pad); + eim_write_32(IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK, (uint32_t *)®_pad); } @@ -174,7 +175,7 @@ void _eim_setup_ccm() struct CCM_CCGR6 ccm_ccgr6; // read register - eim_read_32(CCM_CCGR6, (unsigned int *)&ccm_ccgr6); + eim_read_32(CCM_CCGR6, (uint32_t *)&ccm_ccgr6); // modify register ccm_ccgr6.cg0_usboh3 = CCM_CGR_ON_EXCEPT_STOP; @@ -197,7 +198,7 @@ void _eim_setup_ccm() ccm_ccgr6.cg15_reserved = 0; // write register - eim_write_32(CCM_CCGR6, (unsigned int *)&ccm_ccgr6); + eim_write_32(CCM_CCGR6, (uint32_t *)&ccm_ccgr6); } @@ -218,16 +219,16 @@ void _eim_setup_eim() struct EIM_EAR ear; // read all the registers - eim_read_32(EIM_CS0GCR1, (unsigned int *)&gcr1); - eim_read_32(EIM_CS0GCR2, (unsigned int *)&gcr2); - eim_read_32(EIM_CS0RCR1, (unsigned int *)&rcr1); - eim_read_32(EIM_CS0RCR2, (unsigned int *)&rcr2); - eim_read_32(EIM_CS0WCR1, (unsigned int *)&wcr1); - eim_read_32(EIM_CS0WCR2, (unsigned int *)&wcr2); + eim_read_32(EIM_CS0GCR1, (uint32_t *)&gcr1); + eim_read_32(EIM_CS0GCR2, (uint32_t *)&gcr2); + eim_read_32(EIM_CS0RCR1, (uint32_t *)&rcr1); + eim_read_32(EIM_CS0RCR2, (uint32_t *)&rcr2); + eim_read_32(EIM_CS0WCR1, (uint32_t *)&wcr1); + eim_read_32(EIM_CS0WCR2, (uint32_t *)&wcr2); - eim_read_32(EIM_WCR, (unsigned int *)&wcr); - eim_read_32(EIM_WIAR, (unsigned int *)&wiar); - eim_read_32(EIM_EAR, (unsigned int *)&ear); + eim_read_32(EIM_WCR, (uint32_t *)&wcr); + eim_read_32(EIM_WIAR, (uint32_t *)&wiar); + eim_read_32(EIM_EAR, (uint32_t *)&ear); // manipulate registers as needed gcr1.csen = 1; // chip select is enabled | @@ -319,38 +320,38 @@ void _eim_setup_eim() //ear.error_addr = x; // read-only | // write modified registers - eim_write_32(EIM_CS0GCR1, (unsigned int *)&gcr1); - eim_write_32(EIM_CS0GCR2, (unsigned int *)&gcr2); - eim_write_32(EIM_CS0RCR1, (unsigned int *)&rcr1); - eim_write_32(EIM_CS0RCR2, (unsigned int *)&rcr2); - eim_write_32(EIM_CS0WCR1, (unsigned int *)&wcr1); - eim_write_32(EIM_CS0WCR2, (unsigned int *)&wcr2); - eim_write_32(EIM_WCR, (unsigned int *)&wcr); - eim_write_32(EIM_WIAR, (unsigned int *)&wiar);/* - eim_write_32(EIM_EAR, (unsigned int *)&ear);*/ + eim_write_32(EIM_CS0GCR1, (uint32_t *)&gcr1); + eim_write_32(EIM_CS0GCR2, (uint32_t *)&gcr2); + eim_write_32(EIM_CS0RCR1, (uint32_t *)&rcr1); + eim_write_32(EIM_CS0RCR2, (uint32_t *)&rcr2); + eim_write_32(EIM_CS0WCR1, (uint32_t *)&wcr1); + eim_write_32(EIM_CS0WCR2, (uint32_t *)&wcr2); + eim_write_32(EIM_WCR, (uint32_t *)&wcr); + eim_write_32(EIM_WIAR, (uint32_t *)&wiar);/* + eim_write_32(EIM_EAR, (uint32_t *)&ear);*/ } //------------------------------------------------------------------------------ -void eim_write_32(off_t offset, unsigned int *pvalue) +void eim_write_32(off_t offset, uint32_t *pvalue) //------------------------------------------------------------------------------ { // calculate memory offset - unsigned int *ptr = (unsigned int *)_eim_calc_offset(offset); + uint32_t *ptr = (uint32_t *)_eim_calc_offset(offset); // write data to memory - memcpy(ptr, pvalue, sizeof(unsigned int)); + memcpy(ptr, pvalue, sizeof(uint32_t)); } //------------------------------------------------------------------------------ -void eim_read_32(off_t offset, unsigned int *pvalue) +void eim_read_32(off_t offset, uint32_t *pvalue) //------------------------------------------------------------------------------ { // calculate memory offset - unsigned int *ptr = (unsigned int *)_eim_calc_offset(offset); + uint32_t *ptr = (uint32_t *)_eim_calc_offset(offset); // read data from memory - memcpy(pvalue, ptr, sizeof(unsigned int)); + memcpy(pvalue, ptr, sizeof(uint32_t)); } diff --git a/sw/test-sha256/novena-eim.h b/sw/test-sha256/novena-eim.h index fdcf5a5..3d29f77 100644 --- a/sw/test-sha256/novena-eim.h +++ b/sw/test-sha256/novena-eim.h @@ -102,26 +102,26 @@ enum IMX6DQ_REGISTER_OFFSET struct IOMUXC_SW_MUX_CTL_PAD_EIM //------------------------------------------------------------------------------ { - unsigned int mux_mode : 3; - unsigned int reserved_3 : 1; - unsigned int sion : 1; - unsigned int reserved_31_5 : 27; + uint32_t mux_mode : 3; + uint32_t reserved_3 : 1; + uint32_t sion : 1; + uint32_t reserved_31_5 : 27; }; //------------------------------------------------------------------------------ struct IOMUXC_SW_PAD_CTL_PAD_EIM //------------------------------------------------------------------------------ { - unsigned int sre : 1; - unsigned int reserved_2_1 : 2; - unsigned int dse : 3; - unsigned int speed : 2; - unsigned int reserved_10_8 : 3; - unsigned int ode : 1; - unsigned int pke : 1; - unsigned int pue : 1; - unsigned int pus : 2; - unsigned int hys : 1; - unsigned int reserved_31_17 : 15; + uint32_t sre : 1; + uint32_t reserved_2_1 : 2; + uint32_t dse : 3; + uint32_t speed : 2; + uint32_t reserved_10_8 : 3; + uint32_t ode : 1; + uint32_t pke : 1; + uint32_t pue : 1; + uint32_t pus : 2; + uint32_t hys : 1; + uint32_t reserved_31_17 : 15; }; @@ -129,25 +129,25 @@ struct IOMUXC_SW_PAD_CTL_PAD_EIM struct CCM_CCGR6 //------------------------------------------------------------------------------ { - unsigned int cg0_usboh3 : 2; - unsigned int cg1_usdhc1 : 2; - unsigned int cg2_usdhc2 : 2; - unsigned int cg3_usdhc3 : 2; + uint32_t cg0_usboh3 : 2; + uint32_t cg1_usdhc1 : 2; + uint32_t cg2_usdhc2 : 2; + uint32_t cg3_usdhc3 : 2; - unsigned int cg3_usdhc4 : 2; - unsigned int cg5_eim_slow : 2; - unsigned int cg6_vdoaxiclk : 2; - unsigned int cg7_vpu : 2; + uint32_t cg3_usdhc4 : 2; + uint32_t cg5_eim_slow : 2; + uint32_t cg6_vdoaxiclk : 2; + uint32_t cg7_vpu : 2; - unsigned int cg8_reserved : 2; - unsigned int cg9_reserved : 2; - unsigned int cg10_reserved : 2; - unsigned int cg11_reserved : 2; + uint32_t cg8_reserved : 2; + uint32_t cg9_reserved : 2; + uint32_t cg10_reserved : 2; + uint32_t cg11_reserved : 2; - unsigned int cg12_reserved : 2; - unsigned int cg13_reserved : 2; - unsigned int cg14_reserved : 2; - unsigned int cg15_reserved : 2; + uint32_t cg12_reserved : 2; + uint32_t cg13_reserved : 2; + uint32_t cg14_reserved : 2; + uint32_t cg15_reserved : 2; }; @@ -155,125 +155,125 @@ struct CCM_CCGR6 struct EIM_CS_GCR1 //------------------------------------------------------------------------------ { - unsigned int csen : 1; - unsigned int swr : 1; - unsigned int srd : 1; - unsigned int mum : 1; - unsigned int wfl : 1; - unsigned int rfl : 1; - unsigned int cre : 1; - unsigned int crep : 1; - unsigned int bl : 3; - unsigned int wc : 1; - unsigned int bcd : 2; - unsigned int bcs : 2; - unsigned int dsz : 3; - unsigned int sp : 1; - unsigned int csrec : 3; - unsigned int aus : 1; - unsigned int gbc : 3; - unsigned int wp : 1; - unsigned int psz : 4; + uint32_t csen : 1; + uint32_t swr : 1; + uint32_t srd : 1; + uint32_t mum : 1; + uint32_t wfl : 1; + uint32_t rfl : 1; + uint32_t cre : 1; + uint32_t crep : 1; + uint32_t bl : 3; + uint32_t wc : 1; + uint32_t bcd : 2; + uint32_t bcs : 2; + uint32_t dsz : 3; + uint32_t sp : 1; + uint32_t csrec : 3; + uint32_t aus : 1; + uint32_t gbc : 3; + uint32_t wp : 1; + uint32_t psz : 4; }; //------------------------------------------------------------------------------ struct EIM_CS_GCR2 //------------------------------------------------------------------------------ { - unsigned int adh : 2; - unsigned int reserved_3_2 : 2; - unsigned int daps : 4; - unsigned int dae : 1; - unsigned int dap : 1; - unsigned int reserved_11_10 : 2; - unsigned int mux16_byp_grant : 1; - unsigned int reserved_31_13 : 19; + uint32_t adh : 2; + uint32_t reserved_3_2 : 2; + uint32_t daps : 4; + uint32_t dae : 1; + uint32_t dap : 1; + uint32_t reserved_11_10 : 2; + uint32_t mux16_byp_grant : 1; + uint32_t reserved_31_13 : 19; }; //------------------------------------------------------------------------------ struct EIM_CS_RCR1 //------------------------------------------------------------------------------ { - unsigned int rcsn : 3; - unsigned int reserved_3 : 1; - unsigned int rcsa : 3; - unsigned int reserved_7 : 1; - unsigned int oen : 3; - unsigned int reserved_11 : 1; - unsigned int oea : 3; - unsigned int reserved_15 : 1; - unsigned int radvn : 3; - unsigned int ral : 1; - unsigned int radva : 3; - unsigned int reserved_23 : 1; - unsigned int rwsc : 6; - unsigned int reserved_31_30 : 2; + uint32_t rcsn : 3; + uint32_t reserved_3 : 1; + uint32_t rcsa : 3; + uint32_t reserved_7 : 1; + uint32_t oen : 3; + uint32_t reserved_11 : 1; + uint32_t oea : 3; + uint32_t reserved_15 : 1; + uint32_t radvn : 3; + uint32_t ral : 1; + uint32_t radva : 3; + uint32_t reserved_23 : 1; + uint32_t rwsc : 6; + uint32_t reserved_31_30 : 2; }; //------------------------------------------------------------------------------ struct EIM_CS_RCR2 //------------------------------------------------------------------------------ { - unsigned int rben : 3; - unsigned int rbe : 1; - unsigned int rbea : 3; - unsigned int reserved_7 : 1; - unsigned int rl : 2; - unsigned int reserved_11_10 : 2; - unsigned int pat : 3; - unsigned int apr : 1; - unsigned int reserved_31_16 : 16; + uint32_t rben : 3; + uint32_t rbe : 1; + uint32_t rbea : 3; + uint32_t reserved_7 : 1; + uint32_t rl : 2; + uint32_t reserved_11_10 : 2; + uint32_t pat : 3; + uint32_t apr : 1; + uint32_t reserved_31_16 : 16; }; //------------------------------------------------------------------------------ struct EIM_CS_WCR1 //------------------------------------------------------------------------------ { - unsigned int wcsn : 3; - unsigned int wcsa : 3; - unsigned int wen : 3; - unsigned int wea : 3; - unsigned int wben : 3; - unsigned int wbea : 3; - unsigned int wadvn : 3; - unsigned int wadva : 3; - unsigned int wwsc : 6; - unsigned int wbed : 1; - unsigned int wal : 1; + uint32_t wcsn : 3; + uint32_t wcsa : 3; + uint32_t wen : 3; + uint32_t wea : 3; + uint32_t wben : 3; + uint32_t wbea : 3; + uint32_t wadvn : 3; + uint32_t wadva : 3; + uint32_t wwsc : 6; + uint32_t wbed : 1; + uint32_t wal : 1; }; //------------------------------------------------------------------------------ struct EIM_CS_WCR2 //------------------------------------------------------------------------------ { - unsigned int wbcdd : 1; - unsigned int reserved_31_1 : 31; + uint32_t wbcdd : 1; + uint32_t reserved_31_1 : 31; }; //------------------------------------------------------------------------------ struct EIM_WCR //------------------------------------------------------------------------------ { - unsigned int bcm : 1; - unsigned int gbcd : 2; - unsigned int reserved_3 : 1; - unsigned int inten : 1; - unsigned int intpol : 1; - unsigned int reserved_7_6 : 2; - unsigned int wdog_en : 1; - unsigned int wdog_limit : 2; - unsigned int reserved_31_11 : 21; + uint32_t bcm : 1; + uint32_t gbcd : 2; + uint32_t reserved_3 : 1; + uint32_t inten : 1; + uint32_t intpol : 1; + uint32_t reserved_7_6 : 2; + uint32_t wdog_en : 1; + uint32_t wdog_limit : 2; + uint32_t reserved_31_11 : 21; }; //------------------------------------------------------------------------------ struct EIM_WIAR //------------------------------------------------------------------------------ { - unsigned int ips_req : 1; - unsigned int ips_ack : 1; - unsigned int irq : 1; - unsigned int errst : 1; - unsigned int aclk_en : 1; - unsigned int reserved_31_5 : 27; + uint32_t ips_req : 1; + uint32_t ips_ack : 1; + uint32_t irq : 1; + uint32_t errst : 1; + uint32_t aclk_en : 1; + uint32_t reserved_31_5 : 27; }; //------------------------------------------------------------------------------ struct EIM_EAR //------------------------------------------------------------------------------ { - unsigned int error_addr : 32; + uint32_t error_addr : 32; }; @@ -281,8 +281,8 @@ struct EIM_EAR // Prototypes //------------------------------------------------------------------------------ int eim_setup (); -void eim_write_32 (off_t, unsigned int *); -void eim_read_32 (off_t, unsigned int *); +void eim_write_32 (off_t, uint32_t *); +void eim_read_32 (off_t, uint32_t *); void _eim_setup_iomuxc (); void _eim_setup_ccm (); -- cgit v1.2.3