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AgeCommit message (Collapse)Author
2015-02-01Added proper file headers to all verilog source files.Joachim Strömbergson
2015-02-01Removed trailing whitespace and ^M.Joachim Strömbergson
2015-02-01Updated the dcm to generate sys_clk at 50 MHz. Added Pavels project files.Joachim Strömbergson
2015-02-01Removed trailing whitespace and DOS ^M.Joachim Strömbergson
2015-01-31Adding all main hw source files and constraints.Joachim Strömbergson