| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-02-02 | update project file paths to .v and .ucf files | Paul Selkirk | |
| 2015-02-02 | Changing to Verilog 2001 style interface. Changed port names to not have ↵ | Joachim Strömbergson | |
| inports called ootput etc. Read and write is better. | |||
| 2015-02-01 | Changed to Verilog 2001 interface. Added ports for Cryptech avalanche noise ↵ | Joachim Strömbergson | |
| board. Fixed layout. | |||
| 2015-02-01 | Added header with license and info to the constraint file. | Joachim Strömbergson | |
| 2015-02-01 | Added proper file headers to all verilog source files. | Joachim Strömbergson | |
| 2015-02-01 | Removed trailing whitespace and ^M. | Joachim Strömbergson | |
| 2015-02-01 | Updated the dcm to generate sys_clk at 50 MHz. Added Pavels project files. | Joachim Strömbergson | |
| 2015-02-01 | Removed trailing whitespace and DOS ^M. | Joachim Strömbergson | |
| 2015-01-31 | Adding all main hw source files and constraints. | Joachim Strömbergson | |
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index : test/novena_base | |
| Cryptech Novena FPGA baseline | git repositories |
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