| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-02-02 | Passes build without any warnings. | Joachim Strömbergson | |
| 2015-02-02 | Added real prefix detection of sha255 core. | Joachim Strömbergson | |
| 2015-02-02 | Changed core_selector to instead use the cryptech sha256 core. | Joachim Strömbergson | |
| 2015-02-02 | Changing to Verilog 2001 style interface. Changed port names to not have ↵ | Joachim Strömbergson | |
| inports called ootput etc. Read and write is better. | |||
| 2015-02-01 | Added proper file headers to all verilog source files. | Joachim Strömbergson | |
| 2015-02-01 | Removed trailing whitespace and ^M. | Joachim Strömbergson | |
| 2015-01-31 | Adding all main hw source files and constraints. | Joachim Strömbergson | |
 |
index : test/novena_base | |
| Cryptech Novena FPGA baseline | git repositories |
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