test/novena_base - Cryptech Novena FPGA baseline

Age	Commit message (Collapse)	Author
2015-02-10	Reformat verilog code for readability.	Paul Selkirk

2015-02-10	First stage of integration cleanup.	Paul Selkirk
	Add local SHA core wrappers, due to the need for registered outputs. Remove unused demo-adder code, and reorganize sw directory.
2015-02-10	Updates from Pavel with new mux.	Paul Selkirk
	1. EIM arbiter was updated to take advantage of 3 additional address lines, that bunnie routed from the CPU to the FPGA. Now we have 19 address lines instead of 16, that means 19-2=17 effective bits when using 32-bit access. 2. In the doc directory there's a draft version of current EIM memory map. 3. I've figured out why you guys could not use read and write signals from the arbiter the way they were supposed to be used. I was wrong when I expected Joachim's cores to have registered outputs. They have a combinatorial output in fact. EIM arbiter's minimum latency is 1 cycle, so we have to register data coming out of cores. I've added these three lines to every core wrapper (sha1.v, sha256.v and sha512.v): reg [31 : 0] tmp_read_data_reg; always @(posedge clk) tmp_read_data_reg <= tmp_read_data; assign read_data = tmp_read_data_reg; 4. Joachim told me, that we are going to have different types of cores (HASH, RNG, CIPHER and so on), so I redesigned EIM multiplexor to have separate modules for every core type. RNG and CIPHER selectors right now are just templates with some dummy registers. Here is what was modified in the HASH multiplexor: 4a. Core number 0 was added. It is not an actual HASH core, but a set of global (board-level) registers. I've added three registers so far: board type, bitstream version and one writeable dummy general-purpose register. 4b. Core instantiation was made conditional to allow selecting of what cores to actually implement. We can have a project that offers a large number of cores, so people can disable unnecessary cores to speed up compile time and to save some slices for something else. 4c. I have disconnected .error() output from cores. As far as I understand it gets asserted when some non-existent register is being addressed. In most projects that I've seen writes to empty regions of memory are discarded and reads return zeroes. If you really need this kind of error checking, please re-connect this output as needed. 4d. core_selector.v has an instruction on how to add new HASH cores to our design. 5. TC11() was added to hash_tester.c to check that we can read global board-level registers and that we have access to segments other than HASH. The last check reads dummy registers from RNG and CIPHER segments (which are just templates now), this effectively tests the 3 new added address bits.
2015-02-05	add all SHA cores (hello coretest_hashes)	Paul Selkirk

2015-02-04	fix a few warnings and one errorsha256_core	Paul Selkirk

2015-02-04	Merge branch 'sha256_core' of git.cryptech.is:test/novena_base into sha256_core	Paul Selkirk

2015-02-04	port hash_tester to this version of novena_eim	Paul Selkirk

2015-02-04	change 'unsigned int' to the more explicit 'uint32_t'	Paul Selkirk

2015-02-04	(1) Adding test code to do single block hash. (2) Adding helper function for ↵	Joachim Strömbergson
	reading data from FPGA registers. (3) Moving eim config to separate function.
2015-02-04	Adding NIST test vectors for single and dual block sha256 tests. Adding ↵	Joachim Strömbergson
	function stubs for tests.
2015-02-04	(1) Adding symbols for all registers in the sha256 api.	Joachim Strömbergson

2015-02-03	(1) Updated core selector with logic to connect sha256. (2) Adding test sw ↵	Joachim Strömbergson
	that is able to talk to the sha256 core and perform a hash operation.
2015-02-03	Adding first base with sha256.	Joachim Strömbergson

2015-02-03	More attempts at getting the addresss decoder to work...	Joachim Strömbergson

2015-02-02	Completed first test program for sha256 core.	Joachim Strömbergson

2015-02-02	Fixed name.	Joachim Strömbergson

2015-02-02	Adding initial version of test code for sha256 core.	Joachim Strömbergson

2015-02-02	Passes build without any warnings.	Joachim Strömbergson

2015-02-02	Added real prefix detection of sha255 core.	Joachim Strömbergson

2015-02-02	Changed core_selector to instead use the cryptech sha256 core.	Joachim Strömbergson

2015-02-02	Changing to Verilog 2001 style interface. Changed port names to not have ↵	Joachim Strömbergson
	inports called ootput etc. Read and write is better.
2015-02-01	Changed to Verilog 2001 interface. Added ports for Cryptech avalanche noise ↵	Joachim Strömbergson
	board. Fixed layout.
2015-02-01	Added header with license and info to the constraint file.	Joachim Strömbergson

2015-02-01	Updated README with more info about the base.	Joachim Strömbergson

2015-02-01	Changed file type.	Joachim Strömbergson

2015-02-01	Added proper file headers to all verilog source files.	Joachim Strömbergson

2015-02-01	Removed trailing whitespace and ^M.	Joachim Strömbergson

2015-02-01	Updated the dcm to generate sys_clk at 50 MHz. Added Pavels project files.	Joachim Strömbergson

2015-02-01	Removed trailing whitespace and DOS ^M.	Joachim Strömbergson

2015-01-31	Adding license for the project.	Joachim Strömbergson

2015-01-31	Adding all main hw source files and constraints.	Joachim Strömbergson

2015-01-31	Removed exe bit on source files.	Joachim Strömbergson

2015-01-31	Adding initial version of the sw parts of the baseline.	Joachim Strömbergson

2015-01-31	Adding documentation.	Joachim Strömbergson

2015-01-31	Adding readme to explain the contents of the new repo.	Joachim Strömbergson