diff options
Diffstat (limited to 'rtl')
| -rw-r--r-- | rtl/src/verilog/eim_memory.v | 53 | ||||
| -rw-r--r-- | rtl/src/verilog/novena_baseline_top.v | 19 | ||||
| -rw-r--r-- | rtl/src/verilog/rng_selector.v | 92 |
3 files changed, 68 insertions, 96 deletions
diff --git a/rtl/src/verilog/eim_memory.v b/rtl/src/verilog/eim_memory.v index c570ee6..953cff3 100644 --- a/rtl/src/verilog/eim_memory.v +++ b/rtl/src/verilog/eim_memory.v @@ -10,7 +10,7 @@ // // Author: Pavel Shatov // Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: @@ -44,24 +44,27 @@ module eim_memory input wire sys_clk, input wire sys_rst, + input wire noise, + output wire [7 : 0] noise_led, + input wire [16: 0] sys_eim_addr, input wire sys_eim_wr, input wire sys_eim_rd, output wire [31: 0] sys_read_data, input wire [31: 0] sys_write_data ); - - + + /* Three upper bits of address [16:14] are used to select memory segment. * There can be eight segments. So far segment 0 is used for hashes, * segment 1 is reserved for random number generators, segment 2 is reserved * for chiphers. Other segments are not used so far. */ - + /* Every segment has its own memory map, take at look at corresponding * selectors for more information. */ - + //---------------------------------------------------------------- // Segment Decoder //---------------------------------------------------------------- @@ -72,22 +75,22 @@ module eim_memory wire [ 2: 0] addr_segment = sys_eim_addr[16:14]; // 3 upper bits are decoded here wire [13: 0] addr_segment_int = sys_eim_addr[13: 0]; // 14 lower bits are decoded individually // in corresponding segment selectors - + wire [31: 0] segment_hashes_read_data; // data read from HASHES segment wire [31: 0] segment_rngs_read_data; // data read from RNGS segment wire [31: 0] segment_ciphers_read_data; // data read from CIPHERS segment - + wire segment_enable_hashes = (addr_segment == SEGMENT_ADDR_HASHES) ? 1'b1 : 1'b0; // HASHES segment is being addressed wire segment_enable_rngs = (addr_segment == SEGMENT_ADDR_RNGS) ? 1'b1 : 1'b0; // RNGS segment is being addressed wire segment_enable_ciphers = (addr_segment == SEGMENT_ADDR_CIPHERS) ? 1'b1 : 1'b0; // CIPHERS segment is being addressed - - + + //---------------------------------------------------------------- // Output (Read Data) Bus //---------------------------------------------------------------- reg [31: 0] sys_read_data_reg; assign sys_read_data = sys_read_data_reg; - + always @* // case (addr_segment) @@ -96,9 +99,9 @@ module eim_memory SEGMENT_ADDR_CIPHERS: sys_read_data_reg = segment_ciphers_read_data; default: sys_read_data_reg = {32{1'b0}}; endcase - - - + + + //---------------------------------------------------------------- // HASH Core Selector // @@ -117,38 +120,40 @@ module eim_memory // because we have already decoded 3 upper bits earlier, // every segment can have its own address decoder. .sys_eim_wr(sys_eim_wr), - .sys_eim_rd(sys_eim_rd), + .sys_eim_rd(sys_eim_rd), .sys_write_data(sys_write_data), .sys_read_data(segment_hashes_read_data) // output from HASHES segment ); - - + + //---------------------------------------------------------------- // RNG Selector // // This selector is used to map random number generator registers into // EIM address space and select which RNG to send EIM read and - // write operations to. So far there are no RNG cores. + // write operations to. //---------------------------------------------------------------- rng_selector segment_rngs ( .sys_clk(sys_clk), .sys_rst(sys_rst), - .sys_ena(segment_enable_rngs), // only enable active selector + .noise(noise), + .noise_led(noie_led), + .sys_eim_addr(addr_segment_int), // we only connect 14 lower bits of address here, // because we have already decoded 3 upper bits earlier, // every segment can have its own address decoder. .sys_eim_wr(sys_eim_wr), - .sys_eim_rd(sys_eim_rd), + .sys_eim_rd(sys_eim_rd), .sys_write_data(sys_write_data), .sys_read_data(segment_rngs_read_data) // output from RNGS segment ); - - + + //---------------------------------------------------------------- // CIPHER Selector // @@ -167,13 +172,13 @@ module eim_memory // because we have already decoded 3 upper bits earlier, // every segment can have its own address decoder. .sys_eim_wr(sys_eim_wr), - .sys_eim_rd(sys_eim_rd), + .sys_eim_rd(sys_eim_rd), .sys_write_data(sys_write_data), .sys_read_data(segment_ciphers_read_data) // output from CIPHERS segment ); - - + + endmodule diff --git a/rtl/src/verilog/novena_baseline_top.v b/rtl/src/verilog/novena_baseline_top.v index 3499fa3..4bf1fdb 100644 --- a/rtl/src/verilog/novena_baseline_top.v +++ b/rtl/src/verilog/novena_baseline_top.v @@ -56,12 +56,12 @@ module novena_baseline_top input wire eim_bclk, // EIM burst clock. Started by the CPU. input wire eim_cs0_n, // Chip select (active low). inout wire [15 : 0] eim_da, // Bidirectional address and data port. - input wire [18: 16] eim_a, // MSB part of address port. + input wire [18: 16] eim_a, // MSB part of address port. input wire eim_lba_n, // Latch address signal (active low). input wire eim_wr_n, // write enable signal (active low). input wire eim_oe_n, // output enable signal (active low). output wire eim_wait_n, // Data wait signal (active low). - + // Novena utility ports apoptosis_pin, // Hold low to not restart after config. led_pin // LED on edge close to the FPGA. @@ -137,13 +137,16 @@ module novena_baseline_top .sys_clk(sys_clk), .sys_rst(sys_rst), + .noise(ct_noise), + .noise_led(ct_led), + .sys_eim_addr(sys_eim_addr), .sys_eim_wr(sys_eim_wr), .sys_eim_rd(sys_eim_rd), .sys_write_data(sys_eim_dout), .sys_read_data(sys_eim_din) - ); + ); //---------------------------------------------------------------- @@ -160,16 +163,6 @@ module novena_baseline_top .led_out(led_pin) ); - - //---------------------------------------------------------------- - // Cryptech Logic - // - // Logic specific to the Cryptech use of the Novena. - // Currently we just hard wire the LED outputs. - //---------------------------------------------------------------- - assign ct_led = {8{ct_noise}}; - - //---------------------------------------------------------------- // Novena Patch // diff --git a/rtl/src/verilog/rng_selector.v b/rtl/src/verilog/rng_selector.v index f86b3e9..8cb11ad 100644 --- a/rtl/src/verilog/rng_selector.v +++ b/rtl/src/verilog/rng_selector.v @@ -1,16 +1,13 @@ //====================================================================== // // rng_selector.v -// ----------------- -// Top level wrapper that creates the Cryptech coretest system. -// The wrapper contains instances of external interface, coretest -// and the core to be tested. And if more than one core is -// present the wrapper also includes address and data muxes. +// -------------- +// rng selector wrapper for the RNG. // // // Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov // Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: @@ -45,6 +42,9 @@ module rng_selector input wire sys_rst, input wire sys_ena, + input wire noise, + output wire [7 : 0] noise_led, + input wire [13: 0] sys_eim_addr, input wire sys_eim_wr, input wire sys_eim_rd, @@ -52,61 +52,35 @@ module rng_selector input wire [31 : 0] sys_write_data ); - - // - // Output Register - // - reg [31: 0] tmp_read_data; - assign sys_read_data = tmp_read_data; - + wire core_cs; + + asstgn core_cs = sys_ena & (sys_eim_wr | sys_eim_rd); + + assign noise_led = 8'ab; + + trng trng_inst( + .clk(sys_clk), + .reset_n(!sys_rst), + + .avalanche_noise(noise), + + .cs(core_cs), + .we(sys_eim_wr), + .address(sys_eim_addr[11 : 0]), + .write_data(sys_write_data), + .read_data(sys_read_data), + .error(), + . + .entropy_bit(), + .debug(), + .debug_update(), + . + .security_error() + ); - /* So far we have no RNG cores, let's make some dummy 32-bit registers here - * to prevent ISE from complaining that we don't use input ports. - */ - - reg [31: 0] reg_dummy_first; - reg [31: 0] reg_dummy_second; - reg [31: 0] reg_dummy_third; - - always @(posedge sys_clk) - // - if (sys_rst) begin - reg_dummy_first <= {8{4'hA}}; - reg_dummy_second <= {8{4'hB}}; - reg_dummy_third <= {8{4'hC}}; - end else if (sys_ena) begin - // - if (sys_eim_wr) begin - // - // WRITE handler - // - case (sys_eim_addr) - 14'd0: reg_dummy_first <= sys_write_data; - 14'd1: reg_dummy_second <= sys_write_data; - 14'd2: reg_dummy_third <= sys_write_data; - endcase - // - end - // - if (sys_eim_rd) begin - // - // READ handler - // - case (sys_eim_addr) - 14'd0: tmp_read_data <= reg_dummy_first; - 14'd1: tmp_read_data <= reg_dummy_second; - 14'd2: tmp_read_data <= reg_dummy_third; - // - default: - tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes - endcase - // - end - // - end -endmodule +endmodule // rng_selector //====================================================================== -// EOF core_selector.v +// EOF rng_selector.v //====================================================================== |