diff options
Diffstat (limited to 'rtl')
| -rw-r--r-- | rtl/iseconfig/novena_baseline.projectmgr | 170 | ||||
| -rw-r--r-- | rtl/iseconfig/novena_baseline.xise | 411 | ||||
| -rw-r--r-- | rtl/iseconfig/novena_baseline_top.xreport | 215 | ||||
| -rw-r--r-- | rtl/iseconfig/novena_baseline_top_guide.ncd | 3 | ||||
| -rw-r--r-- | rtl/src/ipcore/_xmsgs/pn_parser.xmsgs | 2 | ||||
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm.gise | 2 | ||||
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm.v | 17 | ||||
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm.veo | 2 | ||||
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm.xco | 12 | ||||
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm.xise | 341 | ||||
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm_flist.txt | 1 |
11 files changed, 1150 insertions, 26 deletions
diff --git a/rtl/iseconfig/novena_baseline.projectmgr b/rtl/iseconfig/novena_baseline.projectmgr new file mode 100644 index 0000000..21c43f4 --- /dev/null +++ b/rtl/iseconfig/novena_baseline.projectmgr @@ -0,0 +1,170 @@ +<?xml version='1.0' encoding='utf-8'?>
+<!--This is an ISE project configuration file.-->
+<!--It holds project specific layout data for the projectmgr plugin.-->
+<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
+<Project version="2" owner="projectmgr" name="novena_baseline" >
+ <!--This is an ISE project configuration file.-->
+ <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
+ <ClosedNodes>
+ <ClosedNodesVersion>2</ClosedNodesVersion>
+ <ClosedNode>/novena_baseline_top E:|__DNSSEC|novena_baseline|src|verilog|novena_baseline_top.v/clkmgr - novena_clkmgr</ClosedNode>
+ <ClosedNode>/novena_baseline_top E:|__DNSSEC|novena_baseline|src|verilog|novena_baseline_top.v/core_mux - core_selector</ClosedNode>
+ <ClosedNode>/novena_baseline_top E:|__DNSSEC|novena_baseline|src|verilog|novena_baseline_top.v/eim - eim_arbiter</ClosedNode>
+ <ClosedNode>/novena_baseline_top E:|__DNSSEC|novena_baseline|src|verilog|novena_baseline_top.v/eim - eim_arbiter/eim_cdc - eim_arbiter_cdc</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems>
+ <SelectedItem>novena_baseline_top (E:/__DNSSEC/novena_baseline/src/verilog/novena_baseline_top.v)</SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000148000000020000000000000000000000000200000064ffffffff000000810000000300000002000001480000000100000003000000000000000100000003</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
+ <CurrentItem>novena_baseline_top (E:/__DNSSEC/novena_baseline/src/verilog/novena_baseline_top.v)</CurrentItem>
+ </ItemView>
+ <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ <ClosedNode>Design Utilities</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems>
+ <SelectedItem></SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem></CurrentItem>
+ </ItemView>
+ <ItemView guiview="File" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ </ClosedNodes>
+ <SelectedItems/>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000002d70000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>clkmgr_dcm.xco</CurrentItem>
+ </ItemView>
+ <ItemView guiview="Library" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ <ClosedNode>work</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems/>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>work</CurrentItem>
+ </ItemView>
+ <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ <ClosedNode>Configure Target Device</ClosedNode>
+ <ClosedNode>Design Utilities</ClosedNode>
+ <ClosedNode>Implement Design/Map</ClosedNode>
+ <ClosedNode>Implement Design/Place & Route</ClosedNode>
+ <ClosedNode>Implement Design/Translate</ClosedNode>
+ <ClosedNode>Synthesize - XST</ClosedNode>
+ <ClosedNode>User Constraints</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems>
+ <SelectedItem>Generate Programming File</SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>Generate Programming File</CurrentItem>
+ </ItemView>
+ <ItemView engineview="SynthesisOnly" sourcetype="DESUT_XCO" guiview="Process" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ </ClosedNodes>
+ <SelectedItems>
+ <SelectedItem></SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem></CurrentItem>
+ </ItemView>
+ <SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
+ <CurrentView>Implementation</CurrentView>
+ <ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ <ClosedNode>User Constraints</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems>
+ <SelectedItem></SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem></CurrentItem>
+ </ItemView>
+ <ItemView engineview="SynthesisOnly" sourcetype="DESUT_CDC" guiview="Process" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ </ClosedNodes>
+ <SelectedItems>
+ <SelectedItem></SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem></CurrentItem>
+ </ItemView>
+ <ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
+ <ClosedNodes>
+ <ClosedNodesVersion>2</ClosedNodesVersion>
+ <ClosedNode>/novena_baseline_top E:|__DNSSEC|novena_baseline|src|verilog|novena_baseline_top.v/clkmgr - novena_clkmgr</ClosedNode>
+ <ClosedNode>/novena_baseline_top E:|__DNSSEC|novena_baseline|src|verilog|novena_baseline_top.v/core_mux - core_selector</ClosedNode>
+ <ClosedNode>/novena_baseline_top E:|__DNSSEC|novena_baseline|src|verilog|novena_baseline_top.v/eim - eim_arbiter</ClosedNode>
+ <ClosedNode>/tb_demo_adder E:|__DNSSEC|novena_baseline|src|testbench|tb_demo_adder.v/uut - novena_baseline_top/clkmgr - novena_clkmgr</ClosedNode>
+ <ClosedNode>/tb_demo_adder E:|__DNSSEC|novena_baseline|src|testbench|tb_demo_adder.v/uut - novena_baseline_top/core_mux - core_selector</ClosedNode>
+ <ClosedNode>/tb_demo_adder E:|__DNSSEC|novena_baseline|src|testbench|tb_demo_adder.v/uut - novena_baseline_top/eim - eim_arbiter</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems>
+ <SelectedItem>tb_demo_adder (E:/__DNSSEC/novena_baseline/src/testbench/tb_demo_adder.v)</SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000165000000020000000000000000000000000200000064ffffffff000000810000000300000002000001650000000100000003000000000000000100000003</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
+ <CurrentItem>tb_demo_adder (E:/__DNSSEC/novena_baseline/src/testbench/tb_demo_adder.v)</CurrentItem>
+ </ItemView>
+ <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ <ClosedNode>Design Utilities</ClosedNode>
+ <ClosedNode>ISim Simulator</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems>
+ <SelectedItem></SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem></CurrentItem>
+ </ItemView>
+ <ItemView engineview="BehavioralSim" sourcetype="DESUT_VERILOG" guiview="Process" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ </ClosedNodes>
+ <SelectedItems>
+ <SelectedItem>Simulate Behavioral Model</SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>Simulate Behavioral Model</CurrentItem>
+ </ItemView>
+</Project>
diff --git a/rtl/iseconfig/novena_baseline.xise b/rtl/iseconfig/novena_baseline.xise new file mode 100644 index 0000000..a270ac9 --- /dev/null +++ b/rtl/iseconfig/novena_baseline.xise @@ -0,0 +1,411 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="src/verilog/novena_baseline_top.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> + <association xil_pn:name="Implementation" xil_pn:seqID="10"/> + </file> + <file xil_pn:name="src/verilog/novena_clkmgr.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> + <association xil_pn:name="Implementation" xil_pn:seqID="6"/> + </file> + <file xil_pn:name="src/ipcore/clkmgr_dcm.xco" xil_pn:type="FILE_COREGEN"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> + <association xil_pn:name="Implementation" xil_pn:seqID="5"/> + </file> + <file xil_pn:name="src/verilog/cdc_bus_pulse.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="src/verilog/eim_arbiter.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> + <association xil_pn:name="Implementation" xil_pn:seqID="8"/> + </file> + <file xil_pn:name="src/verilog/demo_adder.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="Implementation" xil_pn:seqID="4"/> + </file> + <file xil_pn:name="src/verilog/eim_da_phy.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> + </file> + <file xil_pn:name="src/verilog/eim_arbiter_cdc.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="3"/> + </file> + <file xil_pn:name="src/ucf/novena_baseline.ucf" xil_pn:type="FILE_UCF"> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + </file> + <file xil_pn:name="src/verilog/core_selector.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> + <association xil_pn:name="Implementation" xil_pn:seqID="9"/> + </file> + <file xil_pn:name="src/testbench/tb_demo_adder.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="71"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="71"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="71"/> + </file> + <file xil_pn:name="src/verilog/eim_indicator.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/> + <association xil_pn:name="Implementation" xil_pn:seqID="7"/> + </file> + <file xil_pn:name="src/ipcore/clkmgr_dcm.xise" xil_pn:type="FILE_COREGENISE"> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + </file> + </files> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + + <properties> + <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> + <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> + <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> + <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/> + <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="src/testbench/tb_demo_adder.wcfg" xil_pn:valueState="non-default"/> + <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> + <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> + <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Drive Done Pin High" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Enable 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File Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> + <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> + <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> + <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> + <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|tb_demo_adder" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DesignName" xil_pn:value="novena_baseline" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-01-27T11:06:17" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A2AC959759B047C584BD6422069D49BE" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + +</project> diff --git a/rtl/iseconfig/novena_baseline_top.xreport b/rtl/iseconfig/novena_baseline_top.xreport new file mode 100644 index 0000000..b2f704c --- /dev/null +++ b/rtl/iseconfig/novena_baseline_top.xreport @@ -0,0 +1,215 @@ +<?xml version='1.0' encoding='UTF-8'?> +<report-views version="2.0" > + <header> + <DateModified>2015-01-29T01:49:55</DateModified> + <ModuleName>novena_baseline_top</ModuleName> + <SummaryTimeStamp>2015-01-28T23:55:16</SummaryTimeStamp> + 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Compilation " /> + <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> + <toc-item title="HDL Analysis" target=" HDL Analysis " /> + <toc-item title="HDL Parsing" target=" HDL Parsing " /> + <toc-item title="HDL Elaboration" target=" HDL Elaboration " /> + <toc-item title="HDL Synthesis" target=" HDL Synthesis " /> + <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" /> + <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" /> + <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" /> + <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " /> + <toc-item title="Partition Report" target=" Partition Report " /> + <toc-item title="Final Report" target=" Final Report " /> + <toc-item title="Design Summary" target=" Design Summary " /> + <toc-item title="Primitive and Black Box Usage" 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/> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="novena_baseline_top.rpt" label="CPLD Fitter Report (Text)" > + <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" /> + <toc-item title="Resources Summary" target="** Mapped Resource Summary **" /> + <toc-item title="Pin Resources" target="** Pin Resources **" /> + <toc-item title="Global Resources" target="** Global Control Resources **" /> + </view> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="novena_baseline_top.tim" label="CPLD Timing Report (Text)" > + <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> + <toc-item title="Performance Summary" target="Performance Summary:" /> + </view> + <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="novena_baseline_top.pwr" label="Power Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Power summary" target="Power summary" /> + <toc-item title="Thermal summary" target="Thermal summary" /> + </view> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="novena_baseline_top.bgn" label="Bitgen Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> + <toc-item title="Final Summary" target="DRC detected" /> + </view> + </viewgroup> + <viewgroup label="Secondary Reports" > + <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> + <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/novena_baseline_top_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/novena_baseline_top_translate.nlf" label="Post-Translate Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="novena_baseline_top_map.map" label="Map Log File" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Design Information" target="Design Information" /> + <toc-item title="Design Summary" target="Design Summary" /> + </view> + <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" /> + <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top_preroute.twr" label="Post-Map Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item 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10c0eNq1W8uS5CoO/Zn7Adi8M6P38xUdwcOOmM3cRS07+t8HAQJhm8zqcvWiu+RjUiCQ4CDDsrDnD6nXx1IEnoWfy8Kfvz+kXB7ssf7KBVa2A74lXKyAS8DZY2Eb/HBBYUWBZ+En/Pf7gweLqlLJ1T9/7kuugXU417D5XNogzErpuENpsXc4l45J928vRCr1cA/xcL/+t4T94SJ7/rP48FD6+c9qVNLhnv/GLf36+d8ISp7/bj4/7Uv+k1pZ/i48v02GlueVlWdeii88wF8vFLwX6R/7lWtaZXymukUy2qQ69f7gfodGxIdbZW0FE7QmVmvImv9N9sDfZI3aD6qTFVW1vqlas4NqvaBqdVf1clTtUbW8pfqDmzrsAn0njQK4oWAdL+7Js/eYDfHqPWkUwX02U9wWBi/7O3R1EaBkERYaAYLvXRWJAJ7dAVWBv2dVWcCYEDUmMAIsqoKSLQIE3zpMIsBGhDcSAYITmESASX2Watsf5rFyjIGlxsDWY+C/Uaff/7MElRxWPtOz6c8Knm1/1vDs+rOA5xIGMUcBRtS29EJ7KrSt7VlBJRvvzws8i/7M4FkWNaqr2Z4tQpNr9uL+CYCuL3rj1Z5f9NYrkwFXS/r+wj1fhXuof2P9u7UfauifZd07YAHgrAMyA703dOqyNnWsOtfhjQB7NJ06QokUruvUoZIPlEjhdfD2nY7dYuwwdotxw9gtxg9jtxhzGrvFLyVyjYDul1dTmduO7VnV5yMXLYYqzMFkpdBk+1WT4xuT3cHk3hPUdn2wvc21Ln6X7e5gu2Zou/us7R5tH02Ob0a59wQ12R5MbmuAC99lcjia7NBk/9bkS0vDwdKIltIOmpvsjybj2uT8t5j8wRkrCwJEU0KfP8C1qmBR8Fn4Cf/9/jB5rll/FbwvX6X3Mh4eyYbyQ1gDfn/oPCfWdzHATzKNWjYC5wWS5RpoaQfrYKZRqyOwBRjaI60gsAE4AqwkgTXAsPi6JXaD89IJBlfBouDpYmp6vZYuphrX5ayK1b6rgkXB08W0BFVW5bCPbOujvb/LfcR8tpoTGPqIudwoS2DoI2ZzaaoE+ijROugjqgT6KFEy6CNBYOijRKdAt0FYk7W9zIYZNth43Rof+zto/KZyaxhBU9s3mdVrgqambyKXDQRNLd8ylbcrQVPDtzW3mxM0tXtbsl6FqOwk46OsWxlW2GzZmu36O2h2DNktA0GBw2TzV0nQ1OzocrMNQVOzYx4Gywiamh3zKKiVoKnZ6V8iQVB4SRQ0/UMKtFYKZAgFamv+SOnb+lzqvGKyNiKRjZeTxbtJQiIxhSrITMCx97IFneA263P5PkOU2MPyLcB+e8vCmQby2gd2QgPNH9JAOUy9lRbO+GDhe2uBCQ1cZzSw87/CBw80ENnfwPoIDQyNBiL7G1gfoYH2LQ2kpO6KD65v+aA48kF1wQdt5iCXfHDVp9UyXhOE8Id80B7WT/M8E0ObA/6SGKbNyLcwBZtX5ktiuJrP2j4hR2HGB1+a7GZ8MG7fZXKc8cHVvjX5NQVuJo+WugM5ss/B5DDjgzF+l8n7jA+u7uYomzfE8Gh7GG3fZsQwhm8mhhBNmQaCj1UhoLDR5cCyOr1nvE/7FtNfIOQFGAociCG8I8RwpXAjhrBOdLgTwyUS+EwMM9yJoVQEPhNDMDjTQDC4CgGFjRJDy1orwyUxzKpY7bsqBBQ2SgxLdGVVEfsoHIkhvCPEkDMCN2JomSMwIYYrgc/EMMOdGEpJ4EYMLbMIO0IMy2yYYY+Nd0diCO8IMaQoEkPLDEEbMVx2gp6IYUYbMZSCoEgMLWvWKEIMywKWYY3NVkdiCO86MVwNQZEYWiYI2ojhEgh6IoYZbcRQrgRtxNCkYDzRIlFpkftidkwc5tpXJIgdkmLLmBQrSTNxYEfykET7RHZsfx74kW/86JAdC88DPzJf5ke28aOBF10mzg78iH8qXxbcjB+pM0cIX8uXmdlo9iRCsDM25L8rTRbCjA0p+1lL3cFSf7DUHhbMcFgw4/NVviz4GT/y35UvC9uMHyn32U6Is054bbt5RZRMiDOi5L8rcRbZjCgp/1XbzedIon2ZQQv7jCj5b8qgSYnZjNQJnU705FDAVFDwKEQU9iE5pDHtkAoQOtFTVgETVMGjEFHYhy+gyIhyozojQhIAztpJgNGewJ0yIMHIcCMYPU8FcKMjxf8rXNIs0Li8mvYUHTSnM7GW5wO4sbyekwyYgQwehYjCPuQk9UY0NWJY/LLCtU17bZPRzYydstWeqgRVnZG2DBpYTYiSInDPoGnMzgVPM2ihjTCmSIM/ZdBCuCBKGW0ZNG0IeiJKGT1n0EKgREkStGXQNPpysDSDFjBLFjBrGewpgxbcBVHKaMugaUnQE1HK6DmDFhwlSoKgPYPG9fFDuqw0yf+lD+lSrJMP6dacsm1/9EVaCj75jm71Xc1i8hndqrua5Sz3KG9p/uAbnuWoSVvMMXLdcfoRfcPcYzKWfERvkygMXDk0IjgKAgU5TKJcdVWXx0gEHhoRHAWBghw+okc8AQIl+zESLjtMPqJHzLdCBf0YCRcdJh/ReRRH71fV+8PfOkbCZt4f757HYDPvj/Ku5pn3w57qnuaZ90MS+84Rkn5UhA3eD0PecOL9/dwHu/Z+GLhyYIRxFAQKg/fzyLuqwfsVUZUPjDCOgkBh8P5+VoRR7+dx7XD3/n5WhFHv53HpMPF+6fIRkiVtkpe2SdbV/yP1f37gjvUTQRj2xq/D5Do83hy3WJ/T7SNElhsirH3NCfADfrF7XG3dU+VUc3YqIQilfvF1edgTSSsnMSzFsYLRa99tB6QTkxiW8q5mM4lhqe9qPp5e09hmd9Jccy+7+YxifzpgZnAg1UnzXjVv495HHza//LABzPkHz9CUeKzRYY2n/heauM7VkYzjNot6kPOTeU/aW6PxUcYZlrrAOn8sfoVo45p55HhCU7tSuR9gf99NSF9nGShXp0qgnSLQn7n6s55Tdh5/ZobDeL5Oi/lnfWeVt3sKPm3WYwXQ2CoYFHYUhvMF0iGVcYLMg9LZDhPO4Fxv2HC0z/XOAZL+Mxb6jxTD0o/i0hGYUIzM5qsZeaOV21QEg8KOwnAuRLqADasp7Gxn2QA6ZDRuODMiPeuDA0VztyZPTu+Wejghb8DK6IQ84avlSHdMme61+FtkX5nJVOnjTeKs7GSqxNzMlzXrGd3BzMfXNe+TsPfuLtnHWNX7QPbV0nFK9iNGjp6QfYWxpyweFcew1GPGRG5d1SXZB1WZ2iuLR8WR7Ot9PDOOgaDscGacd5ieGUfblBnOjJsOU7IPCYPR+20lO/tf8n6+2xnZ3+4RZ767GdmPdzX7GdkPdzWHGdn3N8k+bmmhCkr2g+/4QPYV4v7S+2Hgsq9DP1fBoxAGso8ZHihwRfazKvD1rKoIHoUwkn2Jqhwl+3iRAmBK9gXClpJ9vEgBML0xcU70uDr3s792Y2JGk6H/bt6YUNMbE/td1Xp6Y2K7q9pMb0zEmzcmrMJrAma4MYGRIXAyrPM/khsw9/rGhMQbEwoFjYIZb0yorur6xoTEGxMKBY2CGW9M4OZcqeHGhOwwmf9NuxohhxsTosPDnaF4jABfI2D5WxGg/SQC9nD38k2YBMDu72qOE//f3V3N28T9d3vT+5FAQxXDfaHYcer9uEUBYy+9X3u8HRRQiCgMJ1mECF3Vpfdrj7eDAgoRheEkC8f9SS7ZvV/4DhPvx01OrqB7v3AdpuwH9lJpN/pIdQf0/1D9f71I9vzBeVF59X1xPCYa6UGJElvDeQcG5xvcZci5dxd5zHVm6ZA3OuWLGknzxwk/7cGzW2r7Mn/xlu/YPBRUsXv+Z4miay+fdTlJXeghdUFSExZaqy6zWsspNeFJauLFGQh7/WH46pwkP2V5cCrT8XXG4m03+eOqqHjVbG72fzj0vxK0/1EpF6T/STdI2v/cs8mEq8Nd+08bWexZfdP+7Wj/Ru3Xf2a/nCwLeMHn6/a7Sf5Qq3v2O3awPw05sV+9sV+M9qvJ4qXdLfs/qpsmxu4LdfsBSMnkcIcbFc+Gu6IEJjsFVzfEHBN2caNcj9dUUd0pWNwcWfKBvC1C0JpSo8uFG6yxka42Utp2OSGQ/FkjcwD3r9M7Kdy/ZDtGUMxatiUOKi32xKwYYds/ZXc2mFXgZ29ucTvk1bAzxArB+4o9jrVOJ78ZOPOO/TgcunChqyJp0kImbO2yvHXENGYe6SIwFHDD6SUKuPP0athwWtzrejlwlzycWF3eXrp6QTlXVwT2f+0e2ro=###4488:XlxV32DM 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f30eNq1W0tyJKsO3UwvAJJ/VXgrjuAbcSfvDjx09N4vkAhEOnntMF0D26SKEojU9yCTz1/U+cchwvN/1PMHlcfz16HSg+vwzB+Fhz1Epmj5oIQ//6EkPsgj/6Xk/Hu48vffg6Ty97fjKeQBzz+ksZYKWNM91oLoC2tFgTXZZE3ZlbVrrEXaYv1hvMqD4/OtrJE/fb5T5jOdJzHoeXahuzLfpUbP4p7zD5LplpaDFZ9vPPlHXu35Vo66DurMOihL5ME7pawucQxW5xI0ZrrQHrEisbEqg8qqDgqrPHgvv/KubJOiziy7SrSsEBG5rhCrDIYC2Z+zQyqzgx/kOjtk3r+dseJBH1Q98truMx97ethon/VFqNgO+7DPf4LJ3/9FvcwKK5752Y5nXZ7deJbl2dd3Ec5XFNn4NOZPI+/PWevzsxjPtDzL+u3ozhdbta99bJ6FMHYjbSXYNnNsQ7on1hFWOea30HQl9omq7JceaRDqGowMwlEJdBD4M/Ni5/YOVXk6U6UQSJOFPzWZcX5qsszv6NRkTs7DTQmfLdVmOluq/XS2VNtxttTR04RMPc5pYfAp5rgufMjvmxCIVpZQlyWkBNnEd2XTf5DN3comrwuDUzP0b8lmLksoArLJn743C7I1kYaIWDZ9XRi8qiF/SzZ3XcKCbOq7svmLbOHy3vRzFtLOQtrrDsC/6/RXhPxghJxOtRhCpj7fita0gYaBrYP38qs4VXn6w0pHIaCeV6W77BHp+cXiR39/qBjHZ8GXrxRHbBT6SqhBhtQVBCLbEktSDQB4tinkiENMEaEGlCJCG2gYWBxijOXAaQox6tSqxoq002gDDQM7hZhqAZWVAal1lzqMz6rUpB6UsohcpCa2boohcpGamCo1nl2kJrrOPoAscQyD0FYGbTuyb8ePz8p2oqy7MYiadxNFZU8RNW8m8roXPDfvJZ6nSYDKR4D8OH16JQvYCu9bseOzspXg61Y0opb4e4blhKh5K8HWreC5eSv5JwdlbnPofticFFkIya6F5DRCMsTWkHCsTLQFwlXcI+dzi105Iaqxi3tzycJ6CMkp015a6u0qLc0mt8nardJSZndZ+1VaysxeWspTU8CyBk5LrR905JN40kB3OC0VYOjl5Z1pqbcwcDDwU1pq3WCFfAYPHLGqaam3MHAw8Nhn8AT5p7c4LbV2kIdJ8ySBbHBaas0go7RUZKW/WIA/LUCTF1mACHJhAbKFKXbon1U4QS0MQMZdznGh/zLsck4L9Zd+i/MHM00TyhJI+8sr73Sk/cxAsZaFvdP+8uLOEiyfcxtEGCSs/cLHwQoXZcYgVrUEK6zOQYRBwtrPDAdWCmm/8GGQh/Yz3ckSab/wcpCR9vMjl2Q5ZTrynpr2h6b9GpVkXbMP0OR25ItCxTFfJrCbZPCw8FZdgmRQoGTwayI75XhlwxfGTVtiuvKdtWXpIw8oY/MA+8KjHBn7fCuy1HhcD+tUi3NCc5ZlwkjS+KEQuSdpZ9rVlhmakiUqCcfsgGJ7BfxVDojwVQgWxy58I1YhWGwjQ3IVgsUuMkTUKgTzXWQIkvOyBg7BUQ46LgsgrS3i3iFD5eU1QEjAANwSUVMIjmKwukOGKqsTEBIwALdE1IwMUWAlJmSIDzJGhjq6xXEIjmyQsRMqBdBsAalZgHiZBSyTUB53dWmZhPKwy3qZhHK/y3qZhHK3awFdG+YkFArgQp8sAEIYcQsLMKDvFgYOBnMSCnVTmXBvAQb03cLAwcDPFtB3OyWhUM8WMrIA28lTEhr1IGMLyGnBbAGJNAuQryrDnFqWYZvelDu9soAj7bI2Kws44i5ru7KAI2yWYeDryxrYAowZdJx6gOMu4t6WYa7ln+Wo2wAKMzdBN9zoweq2DHMt/6yszgEUZm6CbrqzrzOHBRg1yKgMA2dfFxgWYOQgTxYQrxZAmwWol1mAX1nAsQtEuOX92LELRLi4tIBdIMKlpQXsAhHg68sakwXEQZ8sAGp7FxcWAPdjLsAgwiDNFhAGq3sLgPsxF2AQYZBmC+j2Ot2PGT/I2AK66U33Y8YNMgYipLhawNEswLwqC9LHwgKcgWLqh+mEZgsDcHqXM1/ov1O7nMVC/Z3c4vzBAM4vS2AgQopBx0AEAOFF2NsMKL+4M9/RDAZQFWgxARGSD1ZY+2vVC6xqvqMZDKAq0GICIgAPrzMHECHZICMgomd3ZYEBRMhjkCcgIseUXNfnH9B+1rTfrrQf9Dx/mV9AAdBjRsLPUAFUrvPJm0B1X+nDqAELKORJLHEVizex3DfEOpZipW2xjlksg+hILDHIk1jqKpZoYvk72Gj2Q/nr7AriUBAs/hTF6TtlX00G6LfvkSG7KKKVVJwjRCzJJlrATQqoKaHctLY3ePHAmZu7vkK4qLf0KmkFSAAHmy9BAQBrl9bnNu9ddyL//wT/GKoPiGYHqlE+GHODjLyC6FHuMAuNcuMaih92UBuodqa4JQJWrcon+pBw9KodffxZBHSCxcUxGbIZLVhaRDiddqMF9BKxiGzx1GTWyNXVsznROaHRNqE6cDalL+LojNPkqfUgI79+yLENnKfokqkf5Qfekm5vaboyZBcgtzbr5G9XMODWIL68kQpGgkEsEOGPsp8WUVJVqffAMKxbyHBl+tuVUHzJssy5e/Oq6x7+pe0MdDDaLVPNnP1CB6PZ5RwWWVbUu5zjIsuKatNxCfAtNOIsq2dfhY5rDAEeiob7HrzWaPdWzrkNoNigEZteT9jKhCnLkohVrSgoFBsUig0apxpDgD+lHlljT74KGdUYAsIY9B1WX9GTLw5th2C7uga3/APa3zrwjPhTOtKbz85WgtuqIX7xfPLPwXt01yBT1riFpgfxun987AbRR44JvQ6VDcpasoJcbL81O5iXoWwqrTAG6jcNSS9RNup2WS9RNrrrsvQSZaN7PutDBECc9Iyydb+gJ5RNhAPoC5RNpWbtGlA2DSibnlG27kr0hLKdSROwqtauAWXTgLLpCWUTAa4j9YSydbegMcomQuslqguMvL27BZWwBbD4xQJas4N5GcpGV97CH7uRxCwMwNNdznah/57scnYrjCHtRj8AVqmbo58d9Cn6QcFE7SL6gdJTUHoKPT/U3brhMuE++oHSU1B6Cj0/1M3RDzBmaqbopwcZRz+weKqn6KcGefL/15v21JodjH6V9uvVTXviu450ddFegJM9zqt79rRrsXp1zZ7opu/v1wp6vmUXiI59v+uxQt77fsDTeMPTzpnnYL5l74ak5b3vBzyNNzztZHUOplt2Zjur6Za9G4XGt+zMdvIERXWj0BMUJYS6an/rMzEvw5eVWGi/3cWXlVxov93Fl5VaaL/dxZeVXmi/3cWXIQsoS2B8GdKAQsf4cm+AU+oeX1bQWqKgtURBx5uaUnABBlYm3OLLClpLFLSWKOh4U3rS/t4zpyTGIcC+Chlpf+9/UwLn/mArhYx9P7s2OqfWY2Lsq3y/tKvcn+zm/tKtcn+ym/tLv8r9yW7uL8Mq9yebuT/rl2oyTP6f+UGfWj0hZZH+3v9LyHUk9DdLAAFkmPx/B0alv/f/EnIdCf3NEkAAGeZWT0hzpMP+n9lBRhbQL96lxf6fmUHG/t/QufZ3pPWYGPf92r/+z9+dTjMt/1bxn9e4Lf4NnbNOi+jDAcB/JVY2SPzAZgfgSGswMP5V4S+SVZ+32+yZjnTV5213OR+rPm+zy3n137dS7/Z5w1VjnP75tgMChX5n/EXY2z7v/OLOYBcpDODCNU7XSB1DKBNu+7wLqxrsCqtzABeukd0af505wh/gAYV8Y/x1gaH9PRPIZFz4Z/pF+1tzgQkv0n6WVlcvYTOOsLS6egm7sDchC+0Pu7A3oQvtD7uwdw9xhE6Ff4eG/gOUINCR###4272:XlxV32DM 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1b38eNpVW1u2xaqq7JKaadS1x2lMEk0H7ucep+8nFFXq/YprioAI+KBWa3/9+ec/ubW/eMR//nP8Cn6w7zj9G8PNxkfx3/87jusv/B3/fj/Fr298o6/7rx8iHh/Nr/WPJv3rP6WP4a+NvxjR91Fvff3rux725ev39d3Ou7d/8B3HP5RV2UgS+vD7+ndQUR9ZOLJoZMFI0+7ZNXhdu2+wKXdtXUdw5dB1/Kp35bf+xWva5EJfUV/Z+2xcGo/bK72/v1Q+1Y+QvWFdMRnRFWnUK34rcZpKz+sKOFEHp5ucrvGXaiCRTcCJbHLpjq6KEcWa1PeiL62+VCP7PinWdyw1saymJhpOdMFy+9qF0y3XfVnb3lXcct7V/l9Xs1GN1vldtKo17CcSuVVPWfXcrBor+rL68t7n8uqSNyLF0fnyJi4O+knCqLKN+vkod4p2rUHysZGhxU9a/JYWw5U/1HVsXc5vLEm9MDhojs01e2VseFc7t67L9XP71nfp1zmn7j7bpERbSvSOMKak/HnV6jJ+Z6DqZ0jujMgPXxh/w6pF9slhcNSjIAAPE15F2y0iA2aXPyft5n5H+3GsmURj38ixTWMHx1Yf+1rWya/J/dnYx8dizKUxL8c0ZJHw0eaP9jmgAUhvpblA0otfJB64aLEhD5OajbUxT+UPkBPE5XblvKsfTHz5Lh5FGM4ZdU3owQoXLVaRw0ca99fknV9j6+sYd27j3HMj4/rXftu42Ye4Pn5JLpC0znGmrai+sPe5J/6WvKGuL+RN3LHEra6CUcca1aVIaBiV1qjV5XoE+eK76eGBfrzqG3ufR7NYfo1prxEhLUpa3LoQ6FfcRslaX8TbqLCNml0I9WNIj7708FA/urqercutGJYsmaq7pcYSNXsqlHjXGBmqI/1efY2ZPR7ot1byXip4oP8udV1bF+zXbY0v+o15MkyCRov6pbCBvUabzmEJ6KqieTSqqTEYEWkM7itP4653V284R5ipn05kDZvYr1twPKJBAHQFTmfgeJ8JqTl6xJcHBvGv5YTj8GRUv53LIh5fDHmDJxSQPiL9ZLf4IP/ja9oV7VEgHSK1iK0lLcGfn+BrGc3kGBN8P4VaeRgiLZxLsJ2xTA52RTTM6ZzYfKHcxxK9+FgUVkQhRVscecNWyISCIxrgWAvNaEKmeBztvI8TRyZFA1mgZJt6F/UwIXSV8h2V2Bhs3EmNosatUYGNj+EwXU+xyZ2NU/xKou9c0fw93xQfD4pHw8R7Y7Bh4r1R1Lg1KngjXQzeeh7+S2tkeDwcVXFa+Bq/QYZH5y/1pdD8Gxre2Yj85dfZyCeFtufHhhT7WZ5zhkkMyblmqRGzGhRRq6Z8sguO6MqzAXO6GpU09dG8bqnKX3LS3MepmUrWJTUSOeNciOEhiQ9/yVmcEw2Fs6OrqnmdnDKW14mDhifJIp/cZLog5YusehSpKulnlBFuTYe//N6mJeCodr2ikRrPK+IsGjZ+SXxkn9+QhuekqWrMX4rMK1WHlK9Vv8iRtNy5aRadcz8rlT9vdp2XfmlFv5wifvWLE3+xG/LKHTF2xe6LvDL2vpkhkNNwyFdiseOSNx66kGUINA4kj8t3rZaOLa/YXdKcwVIuvoOkdhIwiiV8crHkeATLykf0PuwSprQ3vohnY7DxRTwbRY1bo4I3LNDRsED3Xxo3IotmdnU2IjlbyHpDnC1SvZH1SxTDyOEWoC79lM5ZXe2WiIe/XOKTqCEizDZWizASS43UxPnSvF7+UkScNOUkWUGyypwXhVoc8Bc1LupsfueNm0tgfueNVvTLKeJXvzix+c+Q/2Ruxhmbsc0YezDPhu27S9B3snwnYy+26WILTs13PaN010lynbx4mOfUKy6pvhNn34kvv85VnmNbHZJallRsxNbTmMWCGjhpludYcicXl/tbcrkNZ27DF6+7VUd205bbcGpLuG/DifcYNI5b1BAf2hLvoYzdF6H8/Pa+KQWhjMuGlPNQzgzli28fVfcQm5KUuzflLJbN+7F0b6LZh1R78iZ+8XHxF8V/DXiCfW2Kn9d8Z3HEEthmXj1b4jUPlI8LxOq9iXZ/7VnH5PI+BMrBngipfUmFJ3xf84RWDlwqTRp4Zl7IW3qXVPMEbMtYuTfpSHbIA8uS6yeyg56Qf0uue4I1zBNMN0l2vlmPFSZhyoYjQCZW5k2y6OvCz/Eu4fSDIT/QA4z30SLUrGyawQ3QeFx7PyBn+UPWy1V9f5tq7gYX3YA2L4fcQA9nTnurD26QpxsMusHwhPDlZrCzL9j96IH11SHZSB+X6H4gq/+m5FuSx8bFBfcl2D1heE74BIKbfW8/RyEn1Lcuue4JlzyBVgUtPEFvNaAVF9j7DEsuPWEwJ9i5E/xwACU/3EtNwpRNT7jkCTQqiM39z/dYwt0TcPp2T+h7n2QgNs5j08w9YTAhmEKJqzKF+Z2lvs+mmnmC91Xfqzr3rO7rMTbpiw/uLOdJ8Z+y8AT7vjr8V9/W3CVe3dMGRRvp44KwNwTPCD7UF0TRcXuW8i4X3JZgeML3NU8wEmSiT557xMucEMKSi90hMCf4+ZfsPRfdYQmWTrT3s+S6J1jDPMFoeuPBOKiBnGASpmzfHAJzAhoHReBR4HzLEk5PKPOYF/c+6kwffTfN4AloPDQbcsL5yiVe5oQWfptqRxQ1TxvuCXz3LXpudlqtFS/OWeILPcGfEe04M3jghyMUPjC3oNC8vUYByp/Lm19cWm/tiLcfNECJ5Sh1SXU38AdIo8BifNLgBmXIDa4l1dwAlJwl3UHVi3LnJRduYLQwdrmXXLpBoRvYdSjxjOZ+UMb0g2cJhx849Uups4GlOd9niacj3NMRzr1Pt2wuxdiUc0/g64tfxSt1gieUMT1hbMrhwP+dVmEa+86LPCLzLpv4QxPx0Kw6uH3auid4RcdO0/CA6puNnaX94BZnaHoNCD3NBfvLzU+eoJeb+148sCL1t6S6J9y+NVRuNNU3GlyosdG0mJZYuAK6Xl6EQ9ON2H2hLcmLD+xdyxJNZ7i5O1TtNpW7jT+P4N0o/pZ4dwb0VYqdivjDTQhLPi9/YTrDtfdNKb4a16acO8PNDaJqN6rcjWwYEmCL56ab+8KgL4xpeDyxGsUSPrkgOqu2609VvzgE94TW+HjXmNcz38daVFJ4gu8OcdAFBjNxnj6o8HjCxsWf0sIS7HeHwFe8xle8Nrlhr27xWnL9EW/IBYYybdbu0JfgyQUTbueSy7tD0BNe0xNeW/xw7jAJU7bvDnFo/YcSbfbdodzvEr74IARa2/gcEppocD/EfXdKX+EUduLoXX69d3OCFCv8hE3k5GITPiv95IwNK2w3SzMwvvb3eavYGbl1gbSTBEef1hcTWy08i5it/H1kiM0DNs9iYw+PTmy+c15t8YH10WfzR+OY+uAdO236WGmC1CiYxbb3mbL2ZodgO697k2JWtmu1GQ7fqSzqsyltfA7R4OR/zUl3t9wd3XJ3XJbzSm5S+c5IO0lguetdTGC5O9Jyd9wshzp/Sr/FZlwihuVwrCAft9wdabk7LsshVFLKi48b7o7TcH3vM12DtqzzPjYhMFz1NIAvdR2u6rmxOUQCu918WjDGsFulx9XlcTBOSkVVz9vNVuVwd1k8YLYqh6ubw8H5U6qLy7hEC6vVtti41ar8rW7+hnJTimnxcavV6W7h3vtgtVdWq/cmBFY7fbeylxq3Hk/WKR4bm0NdsFqVt32Mu7zLivpG4ubjOTlFuYmRdvbAbPVdTGA2MKEqnLfOlSnmxWZcosF0W1x83G7Nnw3wldPCximei42brRXOKbx7F4L0kNXasYmA1Zq/EeA7DdAgomx8DqrBzCRni148xjstHKWVLb5Q9ExRnmLEXcTwlFYWH1iu8XKOxkxMwS3XFp9xidgt1xYfZriT63gxCV1R3nAtNsxvyj3TUdD1qZpSmJa7NxGwHEScPt5ze5Sr3Bufg9JpOfqKcfaN4fSzDd6zPbmr7JuUNUDcReM5PS4+vjec23DP7XH63Fh8xiUaWO46Fp9pua7vEGNfyHexoeVOZW1u8OiyXdN+caOc7ldgY43jcYBASmFjd1CknyTO6mXS8sPLjt/mqqosOHee50bCLhOIr5f02kbRyGTelnEySDqS/zxneHHgZTUIx5J0rAulnVi+UfHdRs1aJYlxjErHvB4D1VHjLmgWYSkIR750TOUAIinnWOoPXd0qL3mY4PlsFIkUugYmUFwbhapUSe8Q/viVylINJ8rqJ1rjgrNhYoU33S63pryNyHyb5ggcYxNr0Ek16HRsI05addp5VkYuKWb+UcpvKY9Aw6Xm4hdOgKr0JCm6bqnhN4QSdqKqyty8G+IdLvWloZ9vuQFY9QOTiXndrF4Mufchlx6EXwl/WOhLNIns3fZh8/lbw3AoTqprp1v+/tP59sesbhVm3nPw/KcZJl4U4RF232GB+95puu5CTaVUt+e5E+k6M291sFTcVt8P40WLaZXc2dCVx1ezxs0FkD8b92kQY7Ixb7c0D7X07qP0ts1RWh4piFArJ/F9Zh/PHZkJIs/cETcSdnnuyMod70bRyGTepZA7opY/V2rUNY++biCOpDoOP+3U2LZBt9P6NPq8Mr18dgTgpcayjXj06vv6EMmVaswceSmvaa37CZ5gY19cLYShs7jOmxV82F81gTd7zSoxOigu1W+cIdzY+KmR1TjVKGpUNZoalxpiOB41uhpDjVfEQY2kxgBYzrB3Wfi538LeYRWAjnsJZ4N7He0Ucd6IbdZGjIUACAiIQB1WgNIUMs+RQranvY6PIwKwirZstAD6fLRg/NHCYQ8dXoC3nYi/4qTuP4a7o8a3iNsithUEMdbLiKnxxBJexDc+boLfL0wsI6FpOpgAWCVaU9RohV30i9cpSOU5iLbEpn4ANsk7OyBiYkPzH1M2J6ODM6Bmk9jNf0zhmkwQ8RDxQ4aZk1lWiqJ9F63zy5zMMlLSxMOi9WX9Zameta6HiNNGjHX9ZamefWHTNc/onyvedl4ytMiB8/u4dBCn56VCgxl+zIEodyXCIQIbeBmemfhFgJ4tMXmjqlF8PJyxPsSn1odg08q3VDQsBxt8BRM7g279gRIAbDTheQjzPej36frmU3AFV2kIeKMSqEY80afjos3skK6xoO9WXxdPB+0ZQDtsfXOyEbdF1YAB7I6BRgLIM6ku6OQ/8oSex2Hyxr9flBwE7v2EBEwEt/6yIIE/gft+BHMhK/gvfYFkB1xkiI0G5UuNU6Mf/btA4pHUMDRwXUJHfokQZ1uZ8Nf+dUwWRndJGFK0C6lbHwIEXwl/Nash4eOW8F6FPWQgdt+48MVloES3El4V9IYw3wF0kZ9vO3qdmQ8seiDx69H+aKVHJ13UO6E8LuX13fEs9yb/ofxT8m/Jj5T/UP4p+bfkRxfXiSUCxSUel3jUl1JwKP02zmEWip8CXr0kmAaNKsSnF0oJpvFG5AoB/xYIpiExV9EL4kOnnaHjwtBb+BCaUfjEMASsGLqODBXnhp7ih0AcQ/U1PlDGkNUYOk8OFXNmEYZAGW9cGi60N+Bhjvb+cTsDqrQQMhp5aykOTSO+HC/M0U0IKMB5sPDoRVbWXztfuSsfnZNMXPQ821l+ryyGJ9m+qGDc+exe+QyetBZFT8WdSI5KYEXSkhTBD4gImHCJpLUqggp0nv0rD5tJi1h04u08hFWe45JWt+hg1Vndqay3JC17UblB0N1KKG2SPxSh0TrNnuQgRUjWTqhRJfgnyXOK4C+dS1V5N01yqaK7WGdlm5VuSAm0lBdlOwterMO4Hj/p8SNF8jUFoCnJO4tQP6y1dhbAVZCmX7ziEajpPb+useyRaA/AJ3GwtVJsZWk0yc+Lyoed5VUW+MCs0FG84mc3m4wn9CLfJXYBNdrzUNWe2Gn4LqsWQ1jaUOW7zBOdeIohSG2o8l3hN2YNiSWVIYhtqHJi5pFOmM4QnDZUObEwMA+vrSfvScK9ANKS/f/F4OXC3wZhdRJTk99JMu8EBHr5dS7Qy3Vr0a0h6O5zsLDXWdcbgvKGKi/XNeXhXevUjUqokotfYTlO3T8Er0Al3q7guuWqPjkLhQdR6Z248CFIcKgKJcFA3fgPjf7I6I/W5yE85aLpLprukukumS75OyiCKyu4Lr1vBL6qPHwjgNzgS4poE9pYQBPC1H+r2isY8iqDMvcLyDcESw5V0SYs6sMnGn4nmqETA+HLQFSWP8BEBirhGkPAZkFXfClLWgCFU48vKnrP2lnjxfNkSN8M6ayQvvQ+EhjJRBsMAaNDVSRz65oQBiGmV+0euxCKEzOSCYOHwFMLcx6rFgiK5ucVj+RLtcHASCZKCRQvYW+OVgqK5MBIZqESL2ORuCgvWAZGMsFvziyJWdreRYQAzIxk4czAIjuSBJGcFcmXEG2BkcwXlSGIfajar3j66HyrGMLeh6r9iscSSKmcddWsq7B1J2GvJ4GoJ/MFIpgvB/b+gO/ER12K5MBIVmk8K5IvRTL/xcOXhx7T5DFNHlOLjP/Q6I+M/mh9+AsimRENbldZHS4vMfUnpv6k1J/0bzOVa1yHXNaXFJGcFcmXMEyBkXwzkrMi+RKOITCSCY4FRaIXOkg2MJIFEdar4SF8lbBYWZE8n1IDI/lmJGdF8iW4E8E5nYELHkUorqIpsF7RWG9AJPOFcuhfGkLV5iyYFPdmN4uWJXBZEMk3Izkrki+BbwKO5NceyYTvIZWc3BY8kqOf1ZHjGmHOTYjjJnRv83sFYv1UrN+KdQE/BcOcsEhBFF0KM2nrlNIlpW/buSAaEzIh+AIovosCKL4vKHBxuNkABbFfjWisJmBUEwgJiUTA4QnlFax27vgP88SpPHErT0TmiYd54lSeuLXjR+aJh3niVJ64teMTR9SJmgFFlcXqtW3G/KcKt/otq99rD+7cg9d/it2KYILbO9Hc4HGVtTc7RaJ/pGOVGAL35P8B91OkTg==###5084:XlxV32DM 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1088eNrNmkmS5bgNhi/TB+A8KDcd9saLXrjD9gEkUlp2RC3sTUbd3YByeB+U72V2d3nhqgilnn6CxEQQIJli6mnPRwoxOpdiGinnlkY+cos+ttzlGWJ2Ljf5f6SYvW0nb0eq0ktMR845xSa49pk+9nG37e3bGyc5+t/Vh21fU0k+7SLGY1q2+diP/0oHD+Q29K96Crn9UF+3nnxMzn3//lsYeV/cEp9/8yMtdT7924+4hKd/+RGWGp5jjOvvMGBKU1TfvjCi/1SN91t/FCL8oEKphhTDmxoOqKEZNZTdqmG+Dtkx5DytQy+edxVQLwronyqg3lVAPBXzGTf3ebD08/SCN/GLu4nfovUC9/vE9x984L4K4h9SQXzgA/2HVPBC/6ICf6qgDlGAf1FA9P1NAwIcBPYb0ByA4AAEUjQA+QRuvwsbbmjYCZQb0DmmPwBUAuMG7BzDgWI3FAFAI5BvwGHkgsBH5BgTQCYArg4jeQRAM7j1BvhM0V0k4okUIuTYdSJmnERkEvFE6AkO8vtieKtEIGg44D1+W4mQZtuIUAfbIAJF+2HGaUQqkUykE6EOhuENjumnIwKvCSEB2TcimchOxHANXYfIcfZBxBPpRCKRRsTwdhChpDt8J7QdyCRNO0hDHXTDdSZixnFEaO05iUwi1EEnbzvmQlgp6YTviFMQIc1BP5jUwUGuJ3QtU4ZIIkJrT0+EnjgdEcNbJUJJB3wnFvrBaETIwdiI0N9GIEKbDnJQadNBSavhIBMJRCYR+uiAfeJ62MUhbn7xbx/8+aFeP0BtVMAGg5ItE1j4fV47Pm4f3EsWIBmepgHhTiLgZNntmk++LKhfJgDhYfrmTmxcehkPe/mYSr72cLf1niV4yOLvPo4vtPklAdH04Muxsx37Rn2vZa5pvI87BD1Sl15v9O6N/rVlflhJZPZAyvdeDdU7jXAiGFChlhY5iYxHjg97/ZruyF+1oI1unvJWM6mdz7dXvd9aazLXzgy4iiT6TfrPIeVPqjL2/4jmWgXWk+brce5r6Gv5aXGtEaT1Kw9XP7j5cHz31s994cf6CKemvurjo1ZeW75T3tcs7fdZfRyvs+mBl9yr0B9T3o8A9/ooD/ugX96jrH+asn3ig5/pqtwpem60n5c85Sx6JbJeS7QL75/38sL7PEvn/EP91Pd+0g/1U977iT/UT37v5+P6dPPlL/ZX3teQNy3Pc6aokDPK3Je4cGR3mWXK3UsLf5lNNzonUUXH3v54r7q/JpTh7P26PgSM/jZOTvv/eJTXVciMokiUbzI536NkuETXcYmZ5rf2c2q+ngV8HEjUmPQdSKM987cDOZ9HoprcJfNKLl4/IMX0laT12nK7fkANh3w2JWbhjgCyNj8JXNI2sc/lAyvjgJRfloRryyvfGbmlR54qEZ8ZLAGm951Av/Tdrzoxlc5B0qtE65VxU/Cgdkk7dwUaAe5WZAL50vd+VcrOfZmNpFeJ9ivjh9ktupFmVsepEsBgKRG42D2H/foBnp3g2ZllddwJXPQq0xB63di0sYrY4BoybYlAtXn1trjJKyukDe6ezX7FSoUM1oIr1J9nuHDPPayVjBzoY8WMKB5+tEJlJaAG7vDNkqDLjnlZMqrMDjZLwdTvmCGFO4YdIpcOOTrkKCvk6JSDUTDS9oXqq/CnMrkXljgK6/+OvqrHKA1KqdzRaVBKjRikQSmVe3SN+66F1S2UUhtnDAdf4TqJY2wM1xMS1sFgkBA/mqnuE3dxK3cRLA335xKmRmsMUwlhs03yxt2+NrlwcReuMYT5g70xQnnuEPbKPZbQiDD6MoZ2EwTCSoRBgMvAWjh/G8ZZjUbbSoRrX2NvzdAgDG0+UNJCZCUCz9mCI9KIFCJww43eFgppzD5ggTybWQrLIGJoIM/o8BDPvcPRBxHIMxhFPXc8x8rlm7uk46hEViLMh7iDO026w93Y6Zic7PC3uRLZEG/mRq65TMyNvG2FCHWwQQe7p+90rCR7oPd2nnAEem8Hb7vZQ+6FZxzwHW5RHozRIfNYxKQ1CcY+Vg6TAxGylrkp75g5BsezBOcZkng0IxBXTZ7zeGe2370Zq9GDzZmK65ySrhnI5LA8uXCroYILeSFjluoMROYDRfZcsAMzKoGoqEi5PPfhNx4I+ZXlQzEIdLFtBoHpNx7H+I29HQaBIoY3CPQwokHANTeafeQ4DDSCwLhlGgQuxhDkTQlVyHXykLQEg8BEhbwlzr9SDMLeePSVIte8jepJ287k2xzMmROm4gzEI4xMaU0yHIxQOXJOF3M8uHJSr2YsqjyshmrQ/VeOVc1YuRmIY2WqsCYTQVYDmRBCp6grZwYPs301zLMAFcjMQsO8OXcMFLklLCeZjtGY8hmpGlNnhlJBwLkJi82cajRDNOgXLRiIqm2mw2moyF+PFLdyrM5yINRgIFqYqbfv2VCZsSY9t9Mv+s7Y11cD0cKdxu+HoaLxVyYfeRoEwS9bGug9MyyujPXG/zZzqJqov80Uj9GclJtlJQVziG6ydHOGXak/E3+mOe3zBjKpKC9v+GlyUe6JCGSoKPI0566VHe6ORXBdDUTmKzvcvaGionYjcjRj8RpLiBR5NxluNGw0zpJINo7AcpLmN5kSWQ/O1NKVCE/1WRoLst6vdINL4X5xLJkHy1NnEDg6Z70gmNrUqiBQHYOIJFqYAo0cmFVe5DaQSZKigWgk3koRn6KRHMcKZs209yuSSdwPAzE/P5y5r+EJ8VpGYNgc5pLHxPwd3SDMXqZBwMMw3LHCnYYDxj5zjSEw9PEIXxBwzfJfJoKpFak7c4jvD3NpxNTSvAkkECOcM1daDlNjBgPthChV4k0Lz1s6AhnmKVeupGJiGExSEbk/JUtTIrQaaCVE+1ZzM4sLVajdUNEmlZE7stIKZh8nmpldV8M8tVHNnTITKephqKj55rgBxD2u0DK1sRqqvBEyVLyXEpkfCmTkMleKeJUjrs1AzHu5IRp6Nuql93bunsVurhUVdtjNvSLLRjEQb7+t5m4TY1Nk3iuQUdTNKN//80//slsm/93zP7w/Ft+D5Pxx8THWWv0SJZPYn/7m63z65iWMy2KvO/RuEUM/y+fj6SfJaJe9P21RVglFHJB9me69xfetDn+nicSjW5Pi+70mO3s5z1g+NDnQJLdxj5fAgcq818Tfmui/n3/+63N08VjaOsq6rlO+/OV5PvsXj1ikJgtDkpJwRH2EqY+hP1d9VH0UfXS93hf07dDHrj+VImm7pO2StkvaLmu7pO2StsvaLmu7rO2ytpNS6Zsf7un782thupx9B70iVt+gcCaOYZGFcdE4JX4wnn4KksqNppQveZY0EAnbcqiZN3yX1UmAvjTvlta2pfu6rG4ua2vLOtqyhW0Zwv+QgDDFNXeReZf5dfiyqOjHJr7k9KTESZHuvdSi/oyFIYoPhSlWjHpYkKQfqTp3eYj4PmU9I9R2WXTls8grtZv4Vpl18bpXLV4rneosl0JBDN2bsNsP6WWVxEw8Vig2HXfTcUeQXnQzzk/13dmdPmQ03baStbroJm3RtV4fmy4Zx5mSirJlHZCSSjUeg9PEbOhus9ddofMhP7MaJRfRfK5Zi0f9tokf6MFBKJJ6SnQWoIo2JNQdWs5Iky5KEvtI912myEXzp0XE4PMuIGaRHPaCxKHQWLIovu27JHBh6VKWaZ2y9mPZRCnbkL/C0AheHN3J0t2XKZzvUnrswvKpiyBFqNdbemIcNUlV9e+i6uLUBnpIVaQQ9EVSVq9nIDJ3BOh6ermqwUbVhxp2SDbgtXOvvXt1T1kiN932PffZp+5CbaJlsUvwOif01msIR9XMOWp1IupK4pshVa0t+tSN+6IbeQJknXy5nwW29JLVasWr5tWSRQqMUFZ9G8ddPQpLqd+Hdt0Cj29QOM+GJMEViyxiVXFqXdDFjZQV8Yt1lUApK1XQ2aX41Jeiec4vskIs7fmXvS3x+dtenyQgS0v9I8H86ft9wD8CwiMgPgLSIyA/AsojoGpMFG3EUxtV3VD8Li/JS7DIc0lrX5LeN/+gh/Sih/J/qodTqnRKFc8ZlNd71iwvUoQ/IcW5lPz9+VeJwu7pVwnEXoK00x/fRHn6S7xOZu7595BYLH/Fs17+Ro0E+pLF+86Xqj54vvUztdS3Tf3xfJtnXa9vh/qmvmVdytP5ls7woW9FrXe+NbXh+baqJc+3ofY833a1qr5J5BPtnG9RdfQkQv0X6zx+9Q==
\ No newline at end of file diff --git a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs index 2ccce38..8fe7625 100644 --- a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs +++ b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs @@ -8,7 +8,7 @@ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
-<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "E:/__DNSSEC/novena_baseline/src/ipcore/clkmgr_dcm.v" into library work</arg>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "Z:/Sandbox/external/cryptech/test/novena_base/rtl/src/ipcore/tmp/_cg/clkmgr_dcm.v" into library work</arg>
</msg>
</messages>
diff --git a/rtl/src/ipcore/clkmgr_dcm.gise b/rtl/src/ipcore/clkmgr_dcm.gise index ae9097a..ed6d0f7 100644 --- a/rtl/src/ipcore/clkmgr_dcm.gise +++ b/rtl/src/ipcore/clkmgr_dcm.gise @@ -19,7 +19,7 @@ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
- <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="../../../../src/ipcore/clkmgr_dcm.xise"/>
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="clkmgr_dcm.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="clkmgr_dcm.asy" xil_pn:origination="imported"/>
diff --git a/rtl/src/ipcore/clkmgr_dcm.v b/rtl/src/ipcore/clkmgr_dcm.v index b719b86..71477a8 100644 --- a/rtl/src/ipcore/clkmgr_dcm.v +++ b/rtl/src/ipcore/clkmgr_dcm.v @@ -55,7 +55,7 @@ // "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
-// CLK_OUT1____80.000______0.000______50.0______450.000____150.000
+// CLK_OUT1____50.000______0.000______50.0______200.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
@@ -92,12 +92,11 @@ module clkmgr_dcm wire [7:0] status_int;
wire clkfb;
wire clk0;
- wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
- .CLKFX_DIVIDE (5),
- .CLKFX_MULTIPLY (8),
+ .CLKFX_DIVIDE (1),
+ .CLKFX_MULTIPLY (4),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
@@ -116,7 +115,7 @@ module clkmgr_dcm .CLK270 (),
.CLK2X (),
.CLK2X180 (),
- .CLKFX (clkfx),
+ .CLKFX (),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
@@ -133,17 +132,15 @@ module clkmgr_dcm .DSSEN (1'b0));
assign INPUT_CLK_STOPPED = status_int[1];
- assign CLK_VALID = ( ( locked_int == 1'b 1 ) && ( status_int[2:1] == 2'b 0 ) );
+ assign CLK_VALID = ( ( locked_int == 1'b 1 ) && ( status_int[1] == 1'b 0 ) );
// Output buffering
//-----------------------------------
- BUFG clkf_buf
- (.O (clkfb),
- .I (clk0));
+ assign clkfb = CLK_OUT1;
BUFG clkout1_buf
(.O (CLK_OUT1),
- .I (clkfx));
+ .I (clk0));
diff --git a/rtl/src/ipcore/clkmgr_dcm.veo b/rtl/src/ipcore/clkmgr_dcm.veo index fa19d52..c4e1d31 100644 --- a/rtl/src/ipcore/clkmgr_dcm.veo +++ b/rtl/src/ipcore/clkmgr_dcm.veo @@ -54,7 +54,7 @@ // "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
-// CLK_OUT1____80.000______0.000______50.0______450.000____150.000
+// CLK_OUT1____50.000______0.000______50.0______200.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
diff --git a/rtl/src/ipcore/clkmgr_dcm.xco b/rtl/src/ipcore/clkmgr_dcm.xco index 06b89ec..37f1a1d 100644 --- a/rtl/src/ipcore/clkmgr_dcm.xco +++ b/rtl/src/ipcore/clkmgr_dcm.xco @@ -1,7 +1,7 @@ ##############################################################
#
# Xilinx Core Generator version 14.7
-# Date: Wed Jan 28 21:56:02 2015
+# Date: Sun Feb 01 07:49:40 2015
#
##############################################################
#
@@ -70,7 +70,7 @@ CSET clkin2_jitter_ps=100.0 CSET clkin2_ui_jitter=0.010
CSET clkout1_drives=BUFG
CSET clkout1_requested_duty_cycle=50.0
-CSET clkout1_requested_out_freq=80
+CSET clkout1_requested_out_freq=50
CSET clkout1_requested_phase=0.000
CSET clkout2_drives=BUFG
CSET clkout2_requested_duty_cycle=50.0
@@ -107,15 +107,15 @@ CSET component_name=clkmgr_dcm CSET daddr_port=DADDR
CSET dclk_port=DCLK
CSET dcm_clk_feedback=1X
-CSET dcm_clk_out1_port=CLKFX
+CSET dcm_clk_out1_port=CLK0
CSET dcm_clk_out2_port=CLK0
CSET dcm_clk_out3_port=CLK0
CSET dcm_clk_out4_port=CLK0
CSET dcm_clk_out5_port=CLK0
CSET dcm_clk_out6_port=CLK0
CSET dcm_clkdv_divide=2.0
-CSET dcm_clkfx_divide=5
-CSET dcm_clkfx_multiply=8
+CSET dcm_clkfx_divide=1
+CSET dcm_clkfx_multiply=4
CSET dcm_clkgen_clk_out1_port=CLKFX
CSET dcm_clkgen_clk_out2_port=CLKFX
CSET dcm_clkgen_clk_out3_port=CLKFX
@@ -266,4 +266,4 @@ CSET use_status=false MISC pkg_timestamp=2012-05-10T12:44:55Z
# END Extra information
GENERATE
-# CRC: 9fa2003b
+# CRC: d6857c2d
diff --git a/rtl/src/ipcore/clkmgr_dcm.xise b/rtl/src/ipcore/clkmgr_dcm.xise index 6ab49ca..e6b0f8a 100644 --- a/rtl/src/ipcore/clkmgr_dcm.xise +++ b/rtl/src/ipcore/clkmgr_dcm.xise @@ -16,11 +16,11 @@ <files> <file xil_pn:name="clkmgr_dcm.ucf" xil_pn:type="FILE_UCF"> - <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> </file> <file xil_pn:name="clkmgr_dcm.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> - <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + <association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/> @@ -28,30 +28,359 @@ </files> <properties> + <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> + <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> + <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/> + <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> + <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> + <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/> + <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/> + <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/> <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> - <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> + <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/> + <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> + <property 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<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/> + <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> + <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> + <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/> + <property 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Options Map" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Output File Name" xil_pn:value="clkmgr_dcm" xil_pn:valueState="default"/> + <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/> + <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> + <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> + <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> + <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> + <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="clkmgr_dcm_map.v" xil_pn:valueState="default"/> + <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="clkmgr_dcm_timesim.v" xil_pn:valueState="default"/> + <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="clkmgr_dcm_synthesis.v" xil_pn:valueState="default"/> + <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="clkmgr_dcm_translate.v" xil_pn:valueState="default"/> + <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> + <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> + <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/> + <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/> + <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> + <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> + <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> + <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> + <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/> + <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/> + <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/> + <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> + <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> + <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/> + <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/> + <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> + <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> + <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> - <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> + <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> + <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> + <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/> + <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> + <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> + <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/> + <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/> + <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> <!-- --> <!-- The following properties are for internal use only. These should not be modified.--> <!-- --> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="clkmgr_dcm" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> - <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-01-29T01:56:27" xil_pn:valueState="non-default"/> - <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="35ECECEDE6BC496293C4671B28106B0F" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-02-01T08:50:04" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="67BEB73269CA45ADBC7997434CEC13CB" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> </properties> diff --git a/rtl/src/ipcore/clkmgr_dcm_flist.txt b/rtl/src/ipcore/clkmgr_dcm_flist.txt index 33943f8..bd1b2cd 100644 --- a/rtl/src/ipcore/clkmgr_dcm_flist.txt +++ b/rtl/src/ipcore/clkmgr_dcm_flist.txt @@ -2,7 +2,6 @@ _xmsgs\pn_parser.xmsgs
clkmgr_dcm.asy
clkmgr_dcm.gise
-clkmgr_dcm.sym
clkmgr_dcm.ucf
clkmgr_dcm.v
clkmgr_dcm.veo
|