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-rw-r--r--rtl/src/verilog/core_selector.v44
-rw-r--r--rtl/src/verilog/novena_baseline_top.v4
2 files changed, 20 insertions, 28 deletions
diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v
index 629d3b6..8ce2003 100644
--- a/rtl/src/verilog/core_selector.v
+++ b/rtl/src/verilog/core_selector.v
@@ -38,31 +38,23 @@
module core_selector
(
- sys_clk, sys_rst,
- sys_eim_addr, sys_eim_wr, sys_eim_rd,
- sys_eim_dout, sys_eim_din
+ input wire sys_clk,
+ input wire sys_rst,
+
+ input wire [13: 0] sys_eim_addr,
+ input wire sys_eim_wr,
+ input wire sys_eim_rd,
+ output wire [31 : 0] read_data,
+ input wire [31 : 0] write_data
);
//
- // Ports
- //
- input wire sys_clk;
- input wire sys_rst;
-
- input wire [13: 0] sys_eim_addr;
- input wire sys_eim_wr;
- input wire sys_eim_rd;
- input wire [31: 0] sys_eim_dout;
- output wire [31: 0] sys_eim_din;
-
-
- //
// Internal Registers
//
reg [31: 0] reg_x = {32{1'b0}};
reg [31: 0] reg_y = {32{1'b0}};
reg [15: 0] reg_ctl = {16{1'b0}};
- reg [31: 0] sys_eim_din_reg = {32{1'b0}};
+ reg [31: 0] read_data_reg = {32{1'b0}};
//
@@ -95,9 +87,9 @@ module core_selector
end else if (eim_access_write) begin
//
case (sys_eim_addr[1:0])
- ADDER_OFFSET_REG_X: reg_x <= sys_eim_dout;
- ADDER_OFFSET_REG_Y: reg_y <= sys_eim_dout;
- ADDER_OFFSET_REG_SC: reg_ctl <= sys_eim_dout[15: 0];
+ ADDER_OFFSET_REG_X: reg_x <= write_data;
+ ADDER_OFFSET_REG_Y: reg_y <= write_data;
+ ADDER_OFFSET_REG_SC: reg_ctl <= write_data[15 : 0];
endcase
//
end
@@ -111,20 +103,20 @@ module core_selector
always @(posedge sys_clk)
//
- if (sys_rst) sys_eim_din_reg <= {32{1'b0}};
+ if (sys_rst) read_data_reg <= {32{1'b0}};
//
else if (eim_access_read) begin
//
case (sys_eim_addr[1:0])
- ADDER_OFFSET_REG_X: sys_eim_din_reg <= reg_x;
- ADDER_OFFSET_REG_Y: sys_eim_din_reg <= reg_y;
- ADDER_OFFSET_REG_Z: sys_eim_din_reg <= reg_z;
- ADDER_OFFSET_REG_SC: sys_eim_din_reg <= {reg_sts, reg_ctl};
+ ADDER_OFFSET_REG_X: read_data_reg <= reg_x;
+ ADDER_OFFSET_REG_Y: read_data_reg <= reg_y;
+ ADDER_OFFSET_REG_Z: read_data_reg <= reg_z;
+ ADDER_OFFSET_REG_SC: read_data_reg <= {reg_sts, reg_ctl};
endcase
//
end
- assign sys_eim_din = sys_eim_din_reg;
+ assign read_data = read_data_reg;
//
diff --git a/rtl/src/verilog/novena_baseline_top.v b/rtl/src/verilog/novena_baseline_top.v
index d265e67..20bf28d 100644
--- a/rtl/src/verilog/novena_baseline_top.v
+++ b/rtl/src/verilog/novena_baseline_top.v
@@ -140,8 +140,8 @@ module novena_baseline_top
.sys_eim_wr(sys_eim_wr),
.sys_eim_rd(sys_eim_rd),
- .sys_eim_dout(sys_eim_dout),
- .sys_eim_din(sys_eim_din)
+ .write_data(sys_eim_dout),
+ .read_data(sys_eim_din)
);