diff options
Diffstat (limited to 'rtl/src/verilog/sha256.v')
| -rw-r--r-- | rtl/src/verilog/sha256.v | 98 |
1 files changed, 49 insertions, 49 deletions
diff --git a/rtl/src/verilog/sha256.v b/rtl/src/verilog/sha256.v index d6fb133..04048b1 100644 --- a/rtl/src/verilog/sha256.v +++ b/rtl/src/verilog/sha256.v @@ -6,7 +6,7 @@ // a simple memory like interface with 32 bit data access. // // Authors: Joachim Strömbergson, Paul Selkirk -// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are @@ -38,15 +38,15 @@ module sha256( // Clock and reset. - input wire clk, - input wire reset_n, + input wire clk, + input wire reset_n, // Control. - input wire cs, - input wire we, + input wire cs, + input wire we, // Data ports. - input wire [7 : 0] address, + input wire [7 : 0] address, input wire [31 : 0] write_data, output wire [31 : 0] read_data ); @@ -87,8 +87,8 @@ module sha256( reg init_reg; reg next_reg; - reg [31 : 0] tmp_read_data; - reg [31 : 0] tmp_read_data_reg; + reg [31 : 0] tmp_read_data; + reg [31 : 0] tmp_read_data_reg; //---------------------------------------------------------------- // Wires. @@ -150,55 +150,55 @@ module sha256( //---------------------------------------------------------------- always @(posedge clk) begin - init_reg <= 0; - next_reg <= 0; - - if (cs && we) - begin - // write operations - if ((address >= ADDR_BLOCK) && - (address < ADDR_BLOCK + BLOCK_WORDS)) - block_reg[((address - ADDR_BLOCK) * 32)+:32] <= write_data; - else if (address == ADDR_CTRL) - begin - init_reg <= write_data[CTRL_INIT_BIT]; - next_reg <= write_data[CTRL_NEXT_BIT]; - end - end + init_reg <= 0; + next_reg <= 0; + + if (cs && we) + begin + // write operations + if ((address >= ADDR_BLOCK) && + (address < ADDR_BLOCK + BLOCK_WORDS)) + block_reg[((address - ADDR_BLOCK) * 32)+:32] <= write_data; + else if (address == ADDR_CTRL) + begin + init_reg <= write_data[CTRL_INIT_BIT]; + next_reg <= write_data[CTRL_NEXT_BIT]; + end + end end always @* begin - tmp_read_data = 32'h00000000; - - if (cs && !we) - begin - // read operations - if ((address >= ADDR_BLOCK) && - (address < ADDR_BLOCK + BLOCK_WORDS)) - tmp_read_data = block_reg[((address - ADDR_BLOCK) * 32)+:32]; - else if ((address >= ADDR_DIGEST) && - (address < ADDR_DIGEST + DIGEST_WORDS)) - tmp_read_data = digest_reg[((address - ADDR_DIGEST) * 32)+:32]; - else - case (address) - ADDR_NAME0: - tmp_read_data = core_name0; - ADDR_NAME1: - tmp_read_data = core_name1; - ADDR_VERSION: - tmp_read_data = core_version; - ADDR_CTRL: - tmp_read_data = core_ctrl; - ADDR_STATUS: - tmp_read_data = core_status; - endcase - end + tmp_read_data = 32'h00000000; + + if (cs && !we) + begin + // read operations + if ((address >= ADDR_BLOCK) && + (address < ADDR_BLOCK + BLOCK_WORDS)) + tmp_read_data = block_reg[((address - ADDR_BLOCK) * 32)+:32]; + else if ((address >= ADDR_DIGEST) && + (address < ADDR_DIGEST + DIGEST_WORDS)) + tmp_read_data = digest_reg[((address - ADDR_DIGEST) * 32)+:32]; + else + case (address) + ADDR_NAME0: + tmp_read_data = core_name0; + ADDR_NAME1: + tmp_read_data = core_name1; + ADDR_VERSION: + tmp_read_data = core_version; + ADDR_CTRL: + tmp_read_data = core_ctrl; + ADDR_STATUS: + tmp_read_data = core_status; + endcase + end end always @(posedge clk) begin - tmp_read_data_reg <= tmp_read_data; + tmp_read_data_reg <= tmp_read_data; end endmodule // sha256 |