1 files changed, 33 insertions, 59 deletions

diff --git a/rtl/src/verilog/rng_selector.v b/rtl/src/verilog/rng_selector.v
index f86b3e9..8cb11ad 100644
--- a/rtl/src/verilog/rng_selector.v
+++ b/rtl/src/verilog/rng_selector.v
@@ -1,16 +1,13 @@
 //======================================================================
 //
 // rng_selector.v
-// -----------------
-// Top level wrapper that creates the Cryptech coretest system.
-// The wrapper contains instances of external interface, coretest
-// and the core to be tested. And if more than one core is
-// present the wrapper also includes address and data muxes.
+// --------------
+// rng selector wrapper for the RNG.
 //
 //
 // Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov
 // Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
@@ -45,6 +42,9 @@ module rng_selector
    input wire           sys_rst,
    input wire           sys_ena,
 
+   input wire           noise,
+   output wire [7 : 0]  noise_led,
+
    input wire [13: 0]   sys_eim_addr,
    input wire           sys_eim_wr,
    input wire           sys_eim_rd,
@@ -52,61 +52,35 @@ module rng_selector
    input wire [31 : 0]  sys_write_data
    );
 
-   
-   //
-   // Output Register
-   //
-   reg [31: 0]          tmp_read_data;
-   assign sys_read_data = tmp_read_data;
-   
+  wire core_cs;
+
+  asstgn core_cs = sys_ena & (sys_eim_wr | sys_eim_rd);
+
+  assign noise_led = 8'ab;
+
+  trng trng_inst(
+                 .clk(sys_clk),
+                 .reset_n(!sys_rst),
+
+                 .avalanche_noise(noise),
+
+                 .cs(core_cs),
+                 .we(sys_eim_wr),
+                 .address(sys_eim_addr[11 : 0]),
+                 .write_data(sys_write_data),
+                 .read_data(sys_read_data),
+                 .error(),
+                 .
+                 .entropy_bit(),
+                 .debug(),
+                 .debug_update(),
+                 .
+                 .security_error()
+                );
 
-   /* So far we have no RNG cores, let's make some dummy 32-bit registers here
-    * to prevent ISE from complaining that we don't use input ports.
-    */
-   
-   reg [31: 0]          reg_dummy_first;
-   reg [31: 0]          reg_dummy_second;
-   reg [31: 0]          reg_dummy_third;
-   
-   always @(posedge sys_clk)
-     //
-     if (sys_rst) begin
-        reg_dummy_first  <= {8{4'hA}};
-        reg_dummy_second <= {8{4'hB}};
-        reg_dummy_third  <= {8{4'hC}};
-     end else if (sys_ena) begin
-        //
-        if (sys_eim_wr) begin
-           //
-           // WRITE handler
-           //
-           case (sys_eim_addr)
-             14'd0: reg_dummy_first     <= sys_write_data;
-             14'd1: reg_dummy_second    <= sys_write_data;
-             14'd2: reg_dummy_third     <= sys_write_data;
-           endcase
-           //
-        end
-        //
-        if (sys_eim_rd) begin
-           //
-           // READ handler
-           //
-           case (sys_eim_addr)
-             14'd0: tmp_read_data       <= reg_dummy_first;
-             14'd1: tmp_read_data       <= reg_dummy_second;
-             14'd2: tmp_read_data       <= reg_dummy_third;
-             //
-             default:
-               tmp_read_data    <= {32{1'b0}};  // read non-existent locations as zeroes
-           endcase
-           //
-        end
-        //
-     end
 
-endmodule
+endmodule // rng_selector
 
 //======================================================================
-// EOF core_selector.v
+// EOF rng_selector.v
 //======================================================================