diff options
Diffstat (limited to 'rtl/src/verilog/rng_selector.v')
| -rw-r--r-- | rtl/src/verilog/rng_selector.v | 128 |
1 files changed, 63 insertions, 65 deletions
diff --git a/rtl/src/verilog/rng_selector.v b/rtl/src/verilog/rng_selector.v index 7a1fe7c..f86b3e9 100644 --- a/rtl/src/verilog/rng_selector.v +++ b/rtl/src/verilog/rng_selector.v @@ -40,72 +40,70 @@ //====================================================================== module rng_selector - ( - input wire sys_clk, - input wire sys_rst,
- input wire sys_ena, + ( + input wire sys_clk, + input wire sys_rst, + input wire sys_ena, - input wire [13: 0] sys_eim_addr, - input wire sys_eim_wr, - input wire sys_eim_rd, - output wire [31 : 0] sys_read_data, - input wire [31 : 0] sys_write_data - ); -
-
- //
- // Output Register
- //
- reg [31: 0] tmp_read_data;
- assign sys_read_data = tmp_read_data;
-
-
- /* So far we have no RNG cores, let's make some dummy 32-bit registers here
- * to prevent ISE from complaining that we don't use input ports.
- */
-
- reg [31: 0] reg_dummy_first;
- reg [31: 0] reg_dummy_second;
- reg [31: 0] reg_dummy_third;
-
- always @(posedge sys_clk) - // - if (sys_rst) begin
- reg_dummy_first <= {8{4'hA}};
- reg_dummy_second <= {8{4'hB}};
- reg_dummy_third <= {8{4'hC}}; - end else if (sys_ena) begin
- //
- if (sys_eim_wr) begin
- //
- // WRITE handler
- //
- case (sys_eim_addr)
- 14'd0: reg_dummy_first <= sys_write_data;
- 14'd1: reg_dummy_second <= sys_write_data;
- 14'd2: reg_dummy_third <= sys_write_data;
- endcase
- //
- end
- //
- if (sys_eim_rd) begin
- //
- // READ handler
- //
- case (sys_eim_addr)
- 14'd0: tmp_read_data <= reg_dummy_first;
- 14'd1: tmp_read_data <= reg_dummy_second;
- 14'd2: tmp_read_data <= reg_dummy_third; - //
- default: tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
- /* - default: tmp_read_data <= {32{1'bX}}; // don't care what to read from non-existent locations
- */
- endcase
- //
- end
- //
- end + input wire [13: 0] sys_eim_addr, + input wire sys_eim_wr, + input wire sys_eim_rd, + output wire [31 : 0] sys_read_data, + input wire [31 : 0] sys_write_data + ); + + + // + // Output Register + // + reg [31: 0] tmp_read_data; + assign sys_read_data = tmp_read_data; + + + /* So far we have no RNG cores, let's make some dummy 32-bit registers here + * to prevent ISE from complaining that we don't use input ports. + */ + + reg [31: 0] reg_dummy_first; + reg [31: 0] reg_dummy_second; + reg [31: 0] reg_dummy_third; + + always @(posedge sys_clk) + // + if (sys_rst) begin + reg_dummy_first <= {8{4'hA}}; + reg_dummy_second <= {8{4'hB}}; + reg_dummy_third <= {8{4'hC}}; + end else if (sys_ena) begin + // + if (sys_eim_wr) begin + // + // WRITE handler + // + case (sys_eim_addr) + 14'd0: reg_dummy_first <= sys_write_data; + 14'd1: reg_dummy_second <= sys_write_data; + 14'd2: reg_dummy_third <= sys_write_data; + endcase + // + end + // + if (sys_eim_rd) begin + // + // READ handler + // + case (sys_eim_addr) + 14'd0: tmp_read_data <= reg_dummy_first; + 14'd1: tmp_read_data <= reg_dummy_second; + 14'd2: tmp_read_data <= reg_dummy_third; + // + default: + tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes + endcase + // + end + // + end endmodule |