diff options
Diffstat (limited to 'rtl/src/verilog/novena_baseline_top.v')
-rw-r--r-- | rtl/src/verilog/novena_baseline_top.v | 42 |
1 files changed, 4 insertions, 38 deletions
diff --git a/rtl/src/verilog/novena_baseline_top.v b/rtl/src/verilog/novena_baseline_top.v index 63be3a7..f31f209 100644 --- a/rtl/src/verilog/novena_baseline_top.v +++ b/rtl/src/verilog/novena_baseline_top.v @@ -131,11 +131,14 @@ module novena_baseline_top // EIM address space and select which core to send EIM read and // write operations to. //---------------------------------------------------------------- - core_selector mux + core_selector ct_subsystem ( .sys_clk(sys_clk), .sys_rst(sys_rst), + .ct_noise(ct_noise), + .ct_led(ct_led), + .sys_eim_addr(sys_eim_addr), .sys_eim_wr(sys_eim_wr), .sys_eim_rd(sys_eim_rd), @@ -161,43 +164,6 @@ module novena_baseline_top //---------------------------------------------------------------- - // Cryptech Logic - // - // Logic specific to the Cryptech use of the Novena. - // Currently we just sample the noise and drive the LEDs - // with this signal. - //---------------------------------------------------------------- - reg ct_noise_sample0_reg; - reg ct_noise_sample1_reg; - reg [7 : 0] ct_led_reg; - - always @ (posedge sys_clk) - begin - if (sys_rst) - begin - ct_led_reg <= 8'h00; - ct_noise_sample0_reg <= 1'b0; - ct_noise_sample1_reg <= 1'b0; - end - else - begin - ct_noise_sample0_reg <= ct_noise; - ct_noise_sample1_reg <= ct_noise_sample0_reg; - ct_led_reg[0] <= ct_noise_sample1_reg; - ct_led_reg[1] <= ct_noise_sample1_reg; - ct_led_reg[2] <= ct_noise_sample1_reg; - ct_led_reg[3] <= ct_noise_sample1_reg; - ct_led_reg[4] <= ct_noise_sample1_reg; - ct_led_reg[5] <= ct_noise_sample1_reg; - ct_led_reg[6] <= ct_noise_sample1_reg; - ct_led_reg[7] <= ct_noise_sample1_reg; - end - end - - assign ct_led = ct_led_reg; - - - //---------------------------------------------------------------- // Novena Patch // // Patch logic to keep the Novena board happy. |