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-rw-r--r--rtl/src/verilog/eim_da_phy.v74
1 files changed, 32 insertions, 42 deletions
diff --git a/rtl/src/verilog/eim_da_phy.v b/rtl/src/verilog/eim_da_phy.v
index 9ef6042..8a4a8d7 100644
--- a/rtl/src/verilog/eim_da_phy.v
+++ b/rtl/src/verilog/eim_da_phy.v
@@ -6,7 +6,7 @@
//
//
// Author: Pavel Shatov
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -37,48 +37,38 @@
//======================================================================
module eim_da_phy
- (
- buf_io,
- buf_di, buf_ro,
- buf_t
- );
+ #(parameter BUS_WIDTH = 16)
+ (
+ inout wire [BUS_WIDTH-1:0] buf_io, // connect directly to top-level pins
+ input wire [BUS_WIDTH-1:0] buf_di, // drive input (value driven onto pins)
+ output wire [BUS_WIDTH-1:0] buf_ro, // receiver output (value read from pins)
+ input wire buf_t // tristate control (driver is disabled during tristate)
+ );
- //
- // Parameters
- //
- parameter BUS_WIDTH = 16;
-
- //
- // Ports
- //
- inout wire [BUS_WIDTH-1:0] buf_io; // connect directly to top-level pins
- input wire [BUS_WIDTH-1:0] buf_di; // drive input (value driven onto pins)
- output wire [BUS_WIDTH-1:0] buf_ro; // receiver output (value read from pins)
- input wire buf_t; // tristate control (driver is disabled during tristate)
-
- //
- // IOBUFs
- //
- genvar i;
- generate for (i=0; i<BUS_WIDTH; i=i+1)
- begin: eim_da
- //
- IOBUF #
- (
- .IOSTANDARD ("LVCMOS33"),
- .DRIVE (12),
- .SLEW ("FAST")
- )
- IOBUF_inst
- (
- .IO (buf_io[i]),
- .O (buf_ro[i]),
- .I (buf_di[i]),
- .T (buf_t)
- );
- //
- end
- endgenerate
+ //
+ // IOBUFs
+ //
+ genvar i;
+ generate
+ for (i = 0; i < BUS_WIDTH; i = i+1)
+ begin: eim_da
+ //
+ IOBUF #
+ (
+ .IOSTANDARD("LVCMOS33"),
+ .DRIVE(12),
+ .SLEW("FAST")
+ )
+ IOBUF_inst
+ (
+ .IO(buf_io[i]),
+ .O(buf_ro[i]),
+ .I(buf_di[i]),
+ .T(buf_t)
+ );
+ //
+ end
+ endgenerate
endmodule