diff options
Diffstat (limited to 'rtl/src/verilog/eim_arbiter_cdc.v')
| -rw-r--r-- | rtl/src/verilog/eim_arbiter_cdc.v | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/rtl/src/verilog/eim_arbiter_cdc.v b/rtl/src/verilog/eim_arbiter_cdc.v index c9df62e..a0412fe 100644 --- a/rtl/src/verilog/eim_arbiter_cdc.v +++ b/rtl/src/verilog/eim_arbiter_cdc.v @@ -49,11 +49,11 @@ module eim_arbiter_cdc input wire eim_clk; // eim clock input wire eim_req; // eim transaction request output wire eim_ack; // eim transaction acknowledge - input wire [47: 0] eim_din; // data from cpu to fpga (write access) + input wire [50: 0] eim_din; // data from cpu to fpga (write access) output wire [31: 0] eim_dout; // data from fpga to cpu (read access) input wire sys_clk; // user internal clock - output wire [13: 0] sys_addr; // user access address + output wire [16: 0] sys_addr; // user access address output wire sys_wren; // user write flag output wire [31: 0] sys_data_out; // user write data output wire sys_rden; // user read flag @@ -64,11 +64,11 @@ module eim_arbiter_cdc // EIM_CLK -> SYS_CLK Request // wire sys_req; // request pulse in sys_clk clock domain - wire [47: 0] sys_dout; // transaction data in sys_clk clock domain + wire [50: 0] sys_dout; // transaction data in sys_clk clock domain cdc_bus_pulse # ( - .DATA_WIDTH (48) // {write, read, addr, data} + .DATA_WIDTH (51) // {write, read, msb addr, lsb addr, data} ) cdc_eim_sys ( @@ -85,16 +85,16 @@ module eim_arbiter_cdc // // Output Registers // - reg [13: 0] sys_addr_reg = {14{1'bX}}; // - reg sys_wren_reg = 1'b0; // + reg sys_wren_reg = 1'b0; //
+ reg sys_rden_reg = 1'b0; //
+ reg [16: 0] sys_addr_reg = {17{1'bX}}; // reg [31: 0] sys_data_out_reg = {32{1'bX}}; // - reg sys_rden_reg = 1'b0; // - +
+ assign sys_wren = sys_wren_reg;
+ assign sys_rden = sys_rden_reg; assign sys_addr = sys_addr_reg; - assign sys_wren = sys_wren_reg; assign sys_data_out = sys_data_out_reg; - assign sys_rden = sys_rden_reg; - + // // System (User) Clock Access Handler @@ -102,10 +102,10 @@ module eim_arbiter_cdc always @(posedge sys_clk) // if (sys_req) begin // request detected? - sys_wren_reg <= sys_dout[47]; // set write flag if needed - sys_addr_reg <= sys_dout[45:32]; // set operation address + sys_wren_reg <= sys_dout[50]; // set write flag if needed
+ sys_rden_reg <= sys_dout[49]; // set read flag if needed + sys_addr_reg <= sys_dout[48:32]; // set operation address sys_data_out_reg <= sys_dout[31: 0]; // set data to write - sys_rden_reg <= sys_dout[46]; // set read flag if needed end else begin // no request active sys_wren_reg <= 1'b0; // clear write flag sys_rden_reg <= 1'b0; // clear read flag |