diff options
Diffstat (limited to 'rtl/src/verilog/eim_arbiter.v')
| -rw-r--r-- | rtl/src/verilog/eim_arbiter.v | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/rtl/src/verilog/eim_arbiter.v b/rtl/src/verilog/eim_arbiter.v index 3dc6260..d21799f 100644 --- a/rtl/src/verilog/eim_arbiter.v +++ b/rtl/src/verilog/eim_arbiter.v @@ -39,7 +39,7 @@ module eim_arbiter ( - eim_bclk, eim_cs0_n, eim_da, + eim_bclk, eim_cs0_n, eim_da, eim_a, eim_lba_n, eim_wr_n, eim_oe_n, eim_wait_n, @@ -55,7 +55,8 @@ module eim_arbiter // input wire eim_bclk; // | eim bus input wire eim_cs0_n; // | - inout wire [15: 0] eim_da; // | + inout wire [15: 0] eim_da; // |
+ input wire [18:16] eim_a; // | input wire eim_lba_n; // | input wire eim_wr_n; // | input wire eim_oe_n; // | @@ -63,7 +64,7 @@ module eim_arbiter input wire sys_clk; // system clock - output wire [13: 0] sys_addr; // | user bus + output wire [16: 0] sys_addr; // | user bus output wire sys_wren; // | output wire [31: 0] sys_data_out; // | output wire sys_rden; // | @@ -107,7 +108,7 @@ module eim_arbiter localparam EIM_FSM_STATE_READ_DONE = 5'b1_0_111; // transaction complete reg [ 4: 0] eim_fsm_state = EIM_FSM_STATE_INIT; // fsm state - reg [13: 0] eim_addr_latch = {14{1'bX}}; // transaction address + reg [16: 0] eim_addr_latch = {17{1'bX}}; // transaction address reg [15: 0] eim_write_lsb_latch = {16{1'bX}}; // lower 16 bits of data to write /* These flags are used to wake up from INIT state. */ @@ -183,7 +184,7 @@ module eim_arbiter always @(posedge eim_bclk) // if ((eim_fsm_state == EIM_FSM_STATE_INIT) && (eim_write_start_flag || eim_read_start_flag)) - eim_addr_latch <= da_ro[15:2]; + eim_addr_latch <= {eim_a[18:16], da_ro[15:2]}; // @@ -256,10 +257,11 @@ module eim_arbiter // /* This block is used to transfer request data from BCLK clock domain to SYS_CLK clock domain and - * then transfer acknowledge from SYS_CLK to BCLK clock domain in return. Af first 1+1+14+32 = 48 bits - * are transfered, these are: write flag, read flag, address, write data. During read transaction - * some bogus write data is passed, which is not used later anyway. During read requests 32 bits of data - * are returned, during write requests 32 bits of bogus data are returned, that are never used later. + * then transfer acknowledge from SYS_CLK to BCLK clock domain in return. Af first 1+1+3+14+32 = 51 bits + * are transfered, these are: write flag, read flag, msb part of address, lsb part of address, write data. + * During read transaction some bogus write data is passed, which is not used later anyway. During read + * requests 32 bits of data are returned, during write requests 32 bits of bogus data are returned, + * that are never used later. */ eim_arbiter_cdc eim_cdc |