1 files changed, 66 insertions, 0 deletions
diff --git a/rtl/src/verilog/demo_adder.v b/rtl/src/verilog/demo_adder.v
new file mode 100644
index 0000000..a86f114
--- /dev/null
+++ b/rtl/src/verilog/demo_adder.v
@@ -0,0 +1,66 @@
+`timescale 1ns / 1ps
+
+module demo_adder
+	(
+		clk, rst,
+		x, y, z,
+		ctl, sts
+	);
+	
+		//
+		// Ports
+		//
+	input		wire				clk;	// clock
+	input		wire				rst;	// reset
+	
+	input		wire	[31: 0]	x;		// x
+	input		wire	[31: 0]	y;		// y
+	output	wire	[31: 0]	z;		// z = x + y
+	
+	input		wire	[15: 0]	ctl;	// control
+	output	wire	[15: 0]	sts;	// status
+	
+	
+		//
+		// Internal Registers
+		//
+	reg	[31: 0]	z_reg		= {32{1'b0}};
+	reg	[15: 0]	sts_reg	= {16{1'b0}};
+	reg	[15: 0]	ctl_dly	= {16{1'b0}};
+	
+	assign z		= z_reg;
+	assign sts	= sts_reg;
+
+
+		//
+		// Control Logic
+		//
+	always @(posedge clk)
+		//
+		if (rst)	ctl_dly	<= {16{1'b0}};
+		else		ctl_dly	<= ctl;
+		
+		/* This flag is set whenever different value is written to control register. */
+		
+	wire	adder_go = (ctl != ctl_dly) ? 1'b1 : 1'b0;
+	
+	
+		//
+		// Adder Logic
+		//
+	always @(posedge clk)
+		//
+		if (rst)					z_reg	<= {32{1'b0}};
+		else if (adder_go)	z_reg	<= x + y;
+	
+
+		//
+		// Status Logic
+		//
+	always @(posedge clk)
+		//
+		if (rst)					sts_reg	<= {16{1'b0}};
+		else if (adder_go)	sts_reg	<= ctl;
+
+	
+endmodule