diff options
Diffstat (limited to 'rtl/src/verilog/core_selector.v')
| -rw-r--r-- | rtl/src/verilog/core_selector.v | 296 |
1 files changed, 186 insertions, 110 deletions
diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 3f74a26..7479848 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -1,18 +1,21 @@ //====================================================================== // -// core_selector.v -// --------------- -// Core selector Cryptech Novena FPGA framework. +// coretest_hashes.v +// ----------------- +// Top level wrapper that creates the Cryptech coretest system. +// The wrapper contains instances of external interface, coretest +// and the core to be tested. And if more than one core is +// present the wrapper also includes address and data muxes. // // -// Author: Pavel Shatov -// Copyright (c) 2014, NORDUnet A/S All rights reserved. -// +// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov +// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. +// // Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. // // - Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the @@ -37,111 +40,184 @@ //====================================================================== module core_selector - ( - input wire sys_clk, + ( + input wire sys_clk, input wire sys_rst, - input wire [13: 0] sys_eim_addr, + input wire [13: 0] sys_eim_addr, input wire sys_eim_wr, input wire sys_eim_rd, output wire [31 : 0] read_data, - input wire [31 : 0] write_data - ); - - - // - // Parameters - // - localparam ADDER_BASE_ADDR = 6'h00; // upper 6 bits of address - localparam ADDER_OFFSET_X_REG = 8'h00; // X - localparam ADDER_OFFSET_Y_REG = 8'h01; // Y - - - /* This flag detects whether adder core is being addressed. */ - wire eim_access_adder = (sys_eim_addr[13:8] == ADDER_BASE_ADDR) ? 1'b1 : 1'b0; - - /* These flags detect whether write or read access is requested. */ - wire eim_access_write = sys_eim_wr & eim_access_adder; - wire eim_access_read = sys_eim_rd & eim_access_adder; - wire select = eim_access_read | eim_access_write; - -// reg [31 : 0] read_data_reg; -// reg [31 : 0] y_reg; -// reg [31 : 0] x_reg; -// -// // -// // Write Request Handler -// // -// always @(posedge sys_clk) -// // -// if (sys_rst) begin -// x_reg <= 32'hdeaddead; -// y_reg <= 32'hbeefbeef; -// end -// else if (eim_access_write) begin -// case (sys_eim_addr[7:0]) -// ADDER_OFFSET_X_REG: x_reg <= write_data; -// ADDER_OFFSET_Y_REG: y_reg <= write_data; -// endcase -// end -// -// -// // -// // Read Request Handler -// always @(posedge sys_clk) -// // -// if (sys_rst) -// read_data_reg <= 32'h00000000; -// // -// else if (eim_access_read) begin -// // -// case (sys_eim_addr[7:0]) -// ADDER_OFFSET_X_REG: read_data_reg <= x_reg; -// ADDER_OFFSET_Y_REG: read_data_reg <= y_reg; -// endcase -// // -// end - -// assign read_data = read_data_reg; - - - // localparam SHA256_BASE_ADDR = 6'h14; - // - // wire access_sha256 = (sys_eim_addr[13 : 8] == SHA256_BASE_ADDR) ? 1'b1 : 1'b0; - // wire read_access = sys_eim_rd & access_sha256; - // wire write_access = sys_eim_wr & access_sha256; - // wire select = read_access | write_access; - -// reg [31 : 0] read_data_reg; -// wire [31 : 0] sha_read_data; -// -// assign read_data = read_data_reg; -// -// always @ (posedge sys_clk) -// begin -// if (sys_rst) -// begin -// read_data_reg <= 32'h00000000; -// end -// else -// begin -// read_data_reg <= sha_read_data; -// end -// end - - - sha256 sha256_inst( - .clk(sys_clk), - .reset_n(1'b1), - - .cs(eim_access_adder), - .we(sys_eim_wr), - - .address(sys_eim_addr[7 : 0]), - .write_data(write_data), - .read_data(read_data), - .error() - ); + input wire [31 : 0] write_data + ); + + + //---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- + parameter SHA1_ADDR_PREFIX = 6'b000100; // 0x1000 - 0x13ff + parameter SHA256_ADDR_PREFIX = 6'b001000; // 0x2000 - 0x23ff + parameter SHA512_ADDR_PREFIX = 6'b001100; // 0x3000 - 0x33ff + + + //---------------------------------------------------------------- + // Wires and registers + //---------------------------------------------------------------- + wire clk = sys_clk; + wire reset_n = !sys_rst; + wire [13:0] address = sys_eim_addr; + wire cs = sys_eim_wr | sys_eim_rd; + wire we = sys_eim_wr; + + reg [31:0] read_reg; + reg error_reg; + + // sha1 connections. + reg sha1_cs; + reg sha1_we; + reg [7:0] sha1_address; + reg [31:0] sha1_write_data; + wire [31:0] sha1_read_data; + wire sha1_error; + + // sha256 connections. + reg sha256_cs; + reg sha256_we; + reg [7:0] sha256_address; + reg [31:0] sha256_write_data; + wire [31:0] sha256_read_data; + wire sha256_error; + + // sha512 connections. + reg sha512_cs; + reg sha512_we; + reg [7:0] sha512_address; + reg [31:0] sha512_write_data; + wire [31:0] sha512_read_data; + wire sha512_error; + + + //---------------------------------------------------------------- + // Concurrent assignment. + //---------------------------------------------------------------- + assign read_data = read_reg; + + //---------------------------------------------------------------- + // Core instantiations. + //---------------------------------------------------------------- + sha1 sha1( + // Clock and reset. + .clk(clk), + .reset_n(reset_n), + + // Control. + .cs(sha1_cs), + .we(sha1_we), + + // Data ports. + .address(sha1_address), + .write_data(sha1_write_data), + .read_data(sha1_read_data), + .error(sha1_error) + ); + + + sha256 sha256( + // Clock and reset. + .clk(clk), + .reset_n(reset_n), + + // Control. + .cs(sha256_cs), + .we(sha256_we), + + // Data ports. + .address(sha256_address), + .write_data(sha256_write_data), + .read_data(sha256_read_data), + .error(sha256_error) + ); + + + sha512 sha512( + // Clock and reset. + .clk(clk), + .reset_n(reset_n), + + // Control. + .cs(sha512_cs), + .we(sha512_we), + + // Data ports. + .address(sha512_address), + .write_data(sha512_write_data), + .read_data(sha512_read_data), + .error(sha512_error) + ); + + //---------------------------------------------------------------- + // address_mux + // + // Combinational data mux that handles addressing between + // cores using the 32-bit memory like interface. + //---------------------------------------------------------------- + always @* + begin : address_mux + // Default assignments. + sha1_cs = 0; + sha1_we = 0; + sha1_address = 8'h00; + sha1_write_data = 32'h00000000; + + sha256_cs = 0; + sha256_we = 0; + sha256_address = 8'h00; + sha256_write_data = 32'h00000000; + + sha512_cs = 0; + sha512_we = 0; + sha512_address = 8'h00; + sha512_write_data = 32'h00000000; + + // address mux + case (address[13:8]) + SHA1_ADDR_PREFIX: + begin + sha1_cs = 1; + sha1_we = we; + sha1_address = address[7:0]; + sha1_write_data = write_data; + read_reg = sha1_read_data; + error_reg = sha1_error; + end + + SHA256_ADDR_PREFIX: + begin + sha256_cs = 1; + sha256_we = we; + sha256_address = address[7:0]; + sha256_write_data = write_data; + read_reg = sha256_read_data; + error_reg = sha256_error; + end + + SHA512_ADDR_PREFIX: + begin + sha512_cs = 1; + sha512_we = we; + sha512_address = address[7:0]; + sha512_write_data = write_data; + read_reg = sha512_read_data; + error_reg = sha512_error; + end + + default: + begin + read_reg = 32'hZZZZ; + end + endcase + + end // address_mux endmodule |