diff options
Diffstat (limited to 'rtl/src/verilog/core_selector.v')
| -rw-r--r-- | rtl/src/verilog/core_selector.v | 220 |
1 files changed, 110 insertions, 110 deletions
diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 2db2a05..eb6551a 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -1,112 +1,112 @@ -`timescale 1ns / 1ps
-
-module core_selector
- (
- sys_clk, sys_rst,
+`timescale 1ns / 1ps + +module core_selector + ( + sys_clk, sys_rst, sys_eim_addr, sys_eim_wr, sys_eim_rd, - sys_eim_dout, sys_eim_din
- );
-
- //
- // Ports
- //
- input wire sys_clk;
- input wire sys_rst;
-
- input wire [13: 0] sys_eim_addr;
- input wire sys_eim_wr;
+ sys_eim_dout, sys_eim_din + ); + + // + // Ports + // + input wire sys_clk; + input wire sys_rst; + + input wire [13: 0] sys_eim_addr; + input wire sys_eim_wr; input wire sys_eim_rd; - input wire [31: 0] sys_eim_dout;
- output wire [31: 0] sys_eim_din;
-
-
- //
- // Internal Registers
- //
- reg [31: 0] reg_x = {32{1'b0}};
- reg [31: 0] reg_y = {32{1'b0}};
- reg [15: 0] reg_ctl = {16{1'b0}};
- reg [31: 0] sys_eim_din_reg = {32{1'b0}};
-
-
- //
- // Parameters
- //
- localparam ADDER_BASE_ADDR = 12'h321; // upper 12 bits of address
- localparam ADDER_OFFSET_REG_X = 2'd0; // X
- localparam ADDER_OFFSET_REG_Y = 2'd1; // Y
- localparam ADDER_OFFSET_REG_Z = 2'd2; // Z
- localparam ADDER_OFFSET_REG_SC = 2'd3; // {STATUS, CONTROL}
-
-
- /* This flag detects whether adder core is being addressed. */
- wire eim_access_adder = (sys_eim_addr[13:2] == ADDER_BASE_ADDR) ? 1'b1 : 1'b0;
-
- /* These flags detect whether write or read access is requested. */
- wire eim_access_write = sys_eim_wr & eim_access_adder;
- wire eim_access_read = sys_eim_rd & eim_access_adder;
-
-
- //
- // Write Request Handler
- //
- always @(posedge sys_clk)
- //
- if (sys_rst) begin
- reg_x <= {32{1'b0}};
- reg_y <= {32{1'b0}};
- reg_ctl <= {16{1'b0}};
- end else if (eim_access_write) begin
- //
- case (sys_eim_addr[1:0])
- ADDER_OFFSET_REG_X: reg_x <= sys_eim_dout;
- ADDER_OFFSET_REG_Y: reg_y <= sys_eim_dout;
- ADDER_OFFSET_REG_SC: reg_ctl <= sys_eim_dout[15: 0];
- endcase
- //
- end
-
-
- //
- // Read Request Handler
- //
- wire [31: 0] reg_z;
- wire [15: 0] reg_sts;
-
- always @(posedge sys_clk)
- //
- if (sys_rst) sys_eim_din_reg <= {32{1'b0}};
- //
- else if (eim_access_read) begin
- //
- case (sys_eim_addr[1:0])
- ADDER_OFFSET_REG_X: sys_eim_din_reg <= reg_x;
- ADDER_OFFSET_REG_Y: sys_eim_din_reg <= reg_y;
- ADDER_OFFSET_REG_Z: sys_eim_din_reg <= reg_z;
- ADDER_OFFSET_REG_SC: sys_eim_din_reg <= {reg_sts, reg_ctl};
- endcase
- //
- end
-
- assign sys_eim_din = sys_eim_din_reg;
-
-
- //
- // Demo Adder Core
- //
- demo_adder adder_core
- (
- .clk (sys_clk),
- .rst (sys_rst),
-
- .x (reg_x),
- .y (reg_y),
- .z (reg_z),
-
- .ctl (reg_ctl),
- .sts (reg_sts)
- );
-
-
-
-endmodule
+ input wire [31: 0] sys_eim_dout; + output wire [31: 0] sys_eim_din; + + + // + // Internal Registers + // + reg [31: 0] reg_x = {32{1'b0}}; + reg [31: 0] reg_y = {32{1'b0}}; + reg [15: 0] reg_ctl = {16{1'b0}}; + reg [31: 0] sys_eim_din_reg = {32{1'b0}}; + + + // + // Parameters + // + localparam ADDER_BASE_ADDR = 12'h321; // upper 12 bits of address + localparam ADDER_OFFSET_REG_X = 2'd0; // X + localparam ADDER_OFFSET_REG_Y = 2'd1; // Y + localparam ADDER_OFFSET_REG_Z = 2'd2; // Z + localparam ADDER_OFFSET_REG_SC = 2'd3; // {STATUS, CONTROL} + + + /* This flag detects whether adder core is being addressed. */ + wire eim_access_adder = (sys_eim_addr[13:2] == ADDER_BASE_ADDR) ? 1'b1 : 1'b0; + + /* These flags detect whether write or read access is requested. */ + wire eim_access_write = sys_eim_wr & eim_access_adder; + wire eim_access_read = sys_eim_rd & eim_access_adder; + + + // + // Write Request Handler + // + always @(posedge sys_clk) + // + if (sys_rst) begin + reg_x <= {32{1'b0}}; + reg_y <= {32{1'b0}}; + reg_ctl <= {16{1'b0}}; + end else if (eim_access_write) begin + // + case (sys_eim_addr[1:0]) + ADDER_OFFSET_REG_X: reg_x <= sys_eim_dout; + ADDER_OFFSET_REG_Y: reg_y <= sys_eim_dout; + ADDER_OFFSET_REG_SC: reg_ctl <= sys_eim_dout[15: 0]; + endcase + // + end + + + // + // Read Request Handler + // + wire [31: 0] reg_z; + wire [15: 0] reg_sts; + + always @(posedge sys_clk) + // + if (sys_rst) sys_eim_din_reg <= {32{1'b0}}; + // + else if (eim_access_read) begin + // + case (sys_eim_addr[1:0]) + ADDER_OFFSET_REG_X: sys_eim_din_reg <= reg_x; + ADDER_OFFSET_REG_Y: sys_eim_din_reg <= reg_y; + ADDER_OFFSET_REG_Z: sys_eim_din_reg <= reg_z; + ADDER_OFFSET_REG_SC: sys_eim_din_reg <= {reg_sts, reg_ctl}; + endcase + // + end + + assign sys_eim_din = sys_eim_din_reg; + + + // + // Demo Adder Core + // + demo_adder adder_core + ( + .clk (sys_clk), + .rst (sys_rst), + + .x (reg_x), + .y (reg_y), + .z (reg_z), + + .ctl (reg_ctl), + .sts (reg_sts) + ); + + + +endmodule |