diff options
Diffstat (limited to 'rtl/src/verilog/cdc_bus_pulse.v')
| -rw-r--r-- | rtl/src/verilog/cdc_bus_pulse.v | 52 |
1 files changed, 46 insertions, 6 deletions
diff --git a/rtl/src/verilog/cdc_bus_pulse.v b/rtl/src/verilog/cdc_bus_pulse.v index 631506c..6f1fa34 100644 --- a/rtl/src/verilog/cdc_bus_pulse.v +++ b/rtl/src/verilog/cdc_bus_pulse.v @@ -1,4 +1,45 @@ -`timescale 1ns / 1ps +//====================================================================== +// +// cdc_bus_pulse.v +// --------------- +// Clock Domain Crossing handler for the Cryptech Novena +// FPGA framework design. +// +// This module is based on design suggested on page 27 of the +// paper 'Clock Domain Crossing (CDC) Design & Verification Techniques +// Using SystemVerilog' by Clifford E. Cummings (Sunburst Design, Inc.) +// +// +// Author: Pavel Shatov +// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== module cdc_bus_pulse ( @@ -6,11 +47,6 @@ module cdc_bus_pulse dst_clk, dst_dout, dst_pulse ); - /* This module is based on design suggested on page 27 of an article titled - "Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog" - by Clifford E. Cummings (Sunburst Design, Inc.) - */ - // // Parameters // @@ -112,3 +148,7 @@ module cdc_bus_pulse endmodule + +//====================================================================== +// EOF cdc_bus_pulse.v +//====================================================================== |