diff options
Diffstat (limited to 'rtl/src/ipcore/clkmgr_dcm.xco')
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm.xco | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/rtl/src/ipcore/clkmgr_dcm.xco b/rtl/src/ipcore/clkmgr_dcm.xco index 06b89ec..37f1a1d 100644 --- a/rtl/src/ipcore/clkmgr_dcm.xco +++ b/rtl/src/ipcore/clkmgr_dcm.xco @@ -1,7 +1,7 @@ ##############################################################
#
# Xilinx Core Generator version 14.7
-# Date: Wed Jan 28 21:56:02 2015
+# Date: Sun Feb 01 07:49:40 2015
#
##############################################################
#
@@ -70,7 +70,7 @@ CSET clkin2_jitter_ps=100.0 CSET clkin2_ui_jitter=0.010
CSET clkout1_drives=BUFG
CSET clkout1_requested_duty_cycle=50.0
-CSET clkout1_requested_out_freq=80
+CSET clkout1_requested_out_freq=50
CSET clkout1_requested_phase=0.000
CSET clkout2_drives=BUFG
CSET clkout2_requested_duty_cycle=50.0
@@ -107,15 +107,15 @@ CSET component_name=clkmgr_dcm CSET daddr_port=DADDR
CSET dclk_port=DCLK
CSET dcm_clk_feedback=1X
-CSET dcm_clk_out1_port=CLKFX
+CSET dcm_clk_out1_port=CLK0
CSET dcm_clk_out2_port=CLK0
CSET dcm_clk_out3_port=CLK0
CSET dcm_clk_out4_port=CLK0
CSET dcm_clk_out5_port=CLK0
CSET dcm_clk_out6_port=CLK0
CSET dcm_clkdv_divide=2.0
-CSET dcm_clkfx_divide=5
-CSET dcm_clkfx_multiply=8
+CSET dcm_clkfx_divide=1
+CSET dcm_clkfx_multiply=4
CSET dcm_clkgen_clk_out1_port=CLKFX
CSET dcm_clkgen_clk_out2_port=CLKFX
CSET dcm_clkgen_clk_out3_port=CLKFX
@@ -266,4 +266,4 @@ CSET use_status=false MISC pkg_timestamp=2012-05-10T12:44:55Z
# END Extra information
GENERATE
-# CRC: 9fa2003b
+# CRC: d6857c2d
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