diff options
Diffstat (limited to 'rtl/src/ipcore/clkmgr_dcm.v')
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm.v | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/rtl/src/ipcore/clkmgr_dcm.v b/rtl/src/ipcore/clkmgr_dcm.v index b719b86..71477a8 100644 --- a/rtl/src/ipcore/clkmgr_dcm.v +++ b/rtl/src/ipcore/clkmgr_dcm.v @@ -55,7 +55,7 @@ // "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
-// CLK_OUT1____80.000______0.000______50.0______450.000____150.000
+// CLK_OUT1____50.000______0.000______50.0______200.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
@@ -92,12 +92,11 @@ module clkmgr_dcm wire [7:0] status_int;
wire clkfb;
wire clk0;
- wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
- .CLKFX_DIVIDE (5),
- .CLKFX_MULTIPLY (8),
+ .CLKFX_DIVIDE (1),
+ .CLKFX_MULTIPLY (4),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
@@ -116,7 +115,7 @@ module clkmgr_dcm .CLK270 (),
.CLK2X (),
.CLK2X180 (),
- .CLKFX (clkfx),
+ .CLKFX (),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
@@ -133,17 +132,15 @@ module clkmgr_dcm .DSSEN (1'b0));
assign INPUT_CLK_STOPPED = status_int[1];
- assign CLK_VALID = ( ( locked_int == 1'b 1 ) && ( status_int[2:1] == 2'b 0 ) );
+ assign CLK_VALID = ( ( locked_int == 1'b 1 ) && ( status_int[1] == 1'b 0 ) );
// Output buffering
//-----------------------------------
- BUFG clkf_buf
- (.O (clkfb),
- .I (clk0));
+ assign clkfb = CLK_OUT1;
BUFG clkout1_buf
(.O (CLK_OUT1),
- .I (clkfx));
+ .I (clk0));
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