diff options
Diffstat (limited to 'rtl/iseconfig/novena_baseline.xise')
| -rw-r--r-- | rtl/iseconfig/novena_baseline.xise | 108 |
1 files changed, 84 insertions, 24 deletions
diff --git a/rtl/iseconfig/novena_baseline.xise b/rtl/iseconfig/novena_baseline.xise index a1b8766..06ee7dc 100644 --- a/rtl/iseconfig/novena_baseline.xise +++ b/rtl/iseconfig/novena_baseline.xise @@ -16,54 +16,114 @@ <files> <file xil_pn:name="../src/verilog/novena_baseline_top.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> - <association xil_pn:name="Implementation" xil_pn:seqID="10"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/> + <association xil_pn:name="Implementation" xil_pn:seqID="25"/> </file> <file xil_pn:name="../src/verilog/novena_clkmgr.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> - <association xil_pn:name="Implementation" xil_pn:seqID="6"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/> + <association xil_pn:name="Implementation" xil_pn:seqID="21"/> </file> <file xil_pn:name="../src/ipcore/clkmgr_dcm.xco" xil_pn:type="FILE_COREGEN"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> - <association xil_pn:name="Implementation" xil_pn:seqID="5"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/> + <association xil_pn:name="Implementation" xil_pn:seqID="20"/> </file> <file xil_pn:name="../src/verilog/cdc_bus_pulse.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> - <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> + <association xil_pn:name="Implementation" xil_pn:seqID="14"/> </file> <file xil_pn:name="../src/verilog/eim_arbiter.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> - <association xil_pn:name="Implementation" xil_pn:seqID="8"/> - </file> - <file xil_pn:name="../src/verilog/demo_adder.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> - <association xil_pn:name="Implementation" xil_pn:seqID="4"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> + <association xil_pn:name="Implementation" xil_pn:seqID="24"/> </file> <file xil_pn:name="../src/verilog/eim_da_phy.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> - <association xil_pn:name="Implementation" xil_pn:seqID="2"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/> + <association xil_pn:name="Implementation" xil_pn:seqID="16"/> </file> <file xil_pn:name="../src/verilog/eim_arbiter_cdc.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> - <association xil_pn:name="Implementation" xil_pn:seqID="3"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/> + <association xil_pn:name="Implementation" xil_pn:seqID="17"/> </file> <file xil_pn:name="../src/ucf/novena_baseline.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> - <file xil_pn:name="../src/verilog/core_selector.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> - <association xil_pn:name="Implementation" xil_pn:seqID="9"/> - </file> <file xil_pn:name="../src/testbench/tb_demo_adder.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="71"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="71"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="71"/> </file> <file xil_pn:name="../src/verilog/eim_indicator.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/> + <association xil_pn:name="Implementation" xil_pn:seqID="23"/> + </file> + <file xil_pn:name="../src/verilog/core_selector.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/> + <association xil_pn:name="Implementation" xil_pn:seqID="18"/> + </file> + <file xil_pn:name="../../../../core/sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> + <association xil_pn:name="Implementation" xil_pn:seqID="9"/> + </file> + <file xil_pn:name="../../../../core/sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> + <association xil_pn:name="Implementation" xil_pn:seqID="6"/> + </file> + <file xil_pn:name="../src/verilog/sha1.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> + <association xil_pn:name="Implementation" xil_pn:seqID="12"/> + </file> + <file xil_pn:name="../../../../core/sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> + <association xil_pn:name="Implementation" xil_pn:seqID="8"/> + </file> + <file xil_pn:name="../../../../core/sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> + <association xil_pn:name="Implementation" xil_pn:seqID="5"/> + </file> + <file xil_pn:name="../../../../core/sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="Implementation" xil_pn:seqID="4"/> + </file> + <file xil_pn:name="../src/verilog/sha256.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> + <association xil_pn:name="Implementation" xil_pn:seqID="11"/> + </file> + <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="7"/> </file> + <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="3"/> + </file> + <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_k_constants.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> + </file> + <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_w_mem.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="../src/verilog/sha512.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> + <association xil_pn:name="Implementation" xil_pn:seqID="10"/> + </file> + <file xil_pn:name="../src/verilog/eim_memory.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/> + <association xil_pn:name="Implementation" xil_pn:seqID="22"/> + </file> + <file xil_pn:name="../src/verilog/rng_selector.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/> + <association xil_pn:name="Implementation" xil_pn:seqID="15"/> + </file> + <file xil_pn:name="../src/verilog/cipher_selector.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/> + <association xil_pn:name="Implementation" xil_pn:seqID="19"/> + </file> + <file xil_pn:name="../src/verilog/novena_regs.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> + <association xil_pn:name="Implementation" xil_pn:seqID="13"/> + </file> <file xil_pn:name="../src/ipcore/clkmgr_dcm.xise" xil_pn:type="FILE_COREGENISE"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> |