diff options
Diffstat (limited to 'rtl/iseconfig/novena_baseline.xise')
| -rw-r--r-- | rtl/iseconfig/novena_baseline.xise | 34 |
1 files changed, 15 insertions, 19 deletions
diff --git a/rtl/iseconfig/novena_baseline.xise b/rtl/iseconfig/novena_baseline.xise index d07fb76..06ee7dc 100644 --- a/rtl/iseconfig/novena_baseline.xise +++ b/rtl/iseconfig/novena_baseline.xise @@ -9,10 +9,10 @@ <!-- along with the project source files, is sufficient to open and --> <!-- implement in ISE Project Navigator. --> <!-- --> - <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> + <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> </header> - <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> + <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/> <files> <file xil_pn:name="../src/verilog/novena_baseline_top.v" xil_pn:type="FILE_VERILOG"> @@ -35,10 +35,6 @@ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> <association xil_pn:name="Implementation" xil_pn:seqID="24"/> </file> - <file xil_pn:name="../src/verilog/demo_adder.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> - <association xil_pn:name="Implementation" xil_pn:seqID="0"/> - </file> <file xil_pn:name="../src/verilog/eim_da_phy.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/> <association xil_pn:name="Implementation" xil_pn:seqID="16"/> @@ -64,51 +60,51 @@ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/> <association xil_pn:name="Implementation" xil_pn:seqID="18"/> </file> - <file xil_pn:name="../../../sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../core/sha1/src/rtl/sha1_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> <association xil_pn:name="Implementation" xil_pn:seqID="9"/> </file> - <file xil_pn:name="../../../sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../core/sha1/src/rtl/sha1_w_mem.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/> </file> - <file xil_pn:name="../../../sha1/src/rtl/sha1.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../src/verilog/sha1.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> <association xil_pn:name="Implementation" xil_pn:seqID="12"/> </file> - <file xil_pn:name="../../../sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../core/sha256/src/rtl/sha256_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> <association xil_pn:name="Implementation" xil_pn:seqID="8"/> </file> - <file xil_pn:name="../../../sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../core/sha256/src/rtl/sha256_k_constants.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/> </file> - <file xil_pn:name="../../../sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../core/sha256/src/rtl/sha256_w_mem.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/> </file> - <file xil_pn:name="../../../sha256/src/rtl/sha256.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../src/verilog/sha256.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> <association xil_pn:name="Implementation" xil_pn:seqID="11"/> </file> - <file xil_pn:name="../../../sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_core.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="7"/> </file> - <file xil_pn:name="../../../sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_h_constants.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/> </file> - <file xil_pn:name="../../../sha512/src/rtl/sha512_k_constants.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_k_constants.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/> </file> - <file xil_pn:name="../../../sha512/src/rtl/sha512_w_mem.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../../../../core/sha512/src/rtl/sha512_w_mem.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/> </file> - <file xil_pn:name="../../../sha512/src/rtl/sha512.v" xil_pn:type="FILE_VERILOG"> + <file xil_pn:name="../src/verilog/sha512.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> <association xil_pn:name="Implementation" xil_pn:seqID="10"/> </file> @@ -167,7 +163,7 @@ <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |