diff options
| -rw-r--r-- | rtl/src/verilog/core_selector.v | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 092b8ca..4d3a218 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -48,16 +48,22 @@ module core_selector input wire [31 : 0] write_data ); - parameter SHA256_BASE = 6'h14; - wire is_sha256 = ~(sys_eim_addr[13:8] ^ SHA256_BASE); - wire sha256_cs = (is_sha256 & sys_eim_rd) | (is_sha256 & sys_eim_wr); +// parameter SHA256_BASE = 6'h14; +// wire is_sha256 = ~(sys_eim_addr[13:8] ^ SHA256_BASE); +// wire sha256_cs = (is_sha256 & sys_eim_rd) | (is_sha256 & sys_eim_wr); + + localparam SHA256_BASE_ADDR = 6'h14; + wire access_sha256 = (sys_eim_addr[13 : 8] == SHA256_BASE_ADDR) ? 1'b1 : 1'b0; + wire read_access = sys_eim_wr & access_sha256; + wire write_access = sys_eim_rd & access_sha256; + wire select = read_access | write_access; sha256 sha256_inst( .clk(sys_clk), .reset_n(~sys_rst), - .cs(sha256_cs), - .we(sys_eim_wr), + .cs(select), + .we(write_access), .address(sys_eim_addr[7 : 0]), .write_data(write_data), |