diff options
| -rw-r--r-- | rtl/src/verilog/novena_baseline_top.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/rtl/src/verilog/novena_baseline_top.v b/rtl/src/verilog/novena_baseline_top.v index 15e1be4..63be3a7 100644 --- a/rtl/src/verilog/novena_baseline_top.v +++ b/rtl/src/verilog/novena_baseline_top.v @@ -49,8 +49,8 @@ module novena_baseline_top input wire reset_mcu_b_pin, // Cryptech avalanche noise board input and LED outputs - input wire ct_avalanche_noise, - output wire [07 : 0] ct_avalanche_led, + input wire ct_noise, + output wire [07 : 0] ct_led, // EIM interface input wire eim_bclk, // EIM burst clock. Started by the CPU. @@ -181,7 +181,7 @@ module novena_baseline_top end else begin - ct_noise_sample0_reg <= ct_avalanche_noise; + ct_noise_sample0_reg <= ct_noise; ct_noise_sample1_reg <= ct_noise_sample0_reg; ct_led_reg[0] <= ct_noise_sample1_reg; ct_led_reg[1] <= ct_noise_sample1_reg; @@ -194,7 +194,7 @@ module novena_baseline_top end end - assign ct_avalanche_led = ct_led_reg; + assign ct_led = ct_led_reg; //---------------------------------------------------------------- |