diff options
| -rw-r--r-- | rtl/src/verilog/core_selector.v | 95 |
1 files changed, 10 insertions, 85 deletions
diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 8ce2003..7f92e43 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -48,94 +48,19 @@ module core_selector input wire [31 : 0] write_data ); - // - // Internal Registers - // - reg [31: 0] reg_x = {32{1'b0}}; - reg [31: 0] reg_y = {32{1'b0}}; - reg [15: 0] reg_ctl = {16{1'b0}}; - reg [31: 0] read_data_reg = {32{1'b0}}; + sha256 sha256_inst( + .clk(sys_clk), + .reset_n(~sys_rst), - // - // Parameters - // - localparam ADDER_BASE_ADDR = 12'h321; // upper 12 bits of address - localparam ADDER_OFFSET_REG_X = 2'd0; // X - localparam ADDER_OFFSET_REG_Y = 2'd1; // Y - localparam ADDER_OFFSET_REG_Z = 2'd2; // Z - localparam ADDER_OFFSET_REG_SC = 2'd3; // {STATUS, CONTROL} - - - /* This flag detects whether adder core is being addressed. */ - wire eim_access_adder = (sys_eim_addr[13:2] == ADDER_BASE_ADDR) ? 1'b1 : 1'b0; - - /* These flags detect whether write or read access is requested. */ - wire eim_access_write = sys_eim_wr & eim_access_adder; - wire eim_access_read = sys_eim_rd & eim_access_adder; - - - // - // Write Request Handler - // - always @(posedge sys_clk) - // - if (sys_rst) begin - reg_x <= {32{1'b0}}; - reg_y <= {32{1'b0}}; - reg_ctl <= {16{1'b0}}; - end else if (eim_access_write) begin - // - case (sys_eim_addr[1:0]) - ADDER_OFFSET_REG_X: reg_x <= write_data; - ADDER_OFFSET_REG_Y: reg_y <= write_data; - ADDER_OFFSET_REG_SC: reg_ctl <= write_data[15 : 0]; - endcase - // - end - - - // - // Read Request Handler - // - wire [31: 0] reg_z; - wire [15: 0] reg_sts; - - always @(posedge sys_clk) - // - if (sys_rst) read_data_reg <= {32{1'b0}}; - // - else if (eim_access_read) begin - // - case (sys_eim_addr[1:0]) - ADDER_OFFSET_REG_X: read_data_reg <= reg_x; - ADDER_OFFSET_REG_Y: read_data_reg <= reg_y; - ADDER_OFFSET_REG_Z: read_data_reg <= reg_z; - ADDER_OFFSET_REG_SC: read_data_reg <= {reg_sts, reg_ctl}; - endcase - // - end - - assign read_data = read_data_reg; - - - // - // Demo Adder Core - // - demo_adder adder_core - ( - .clk (sys_clk), - .rst (sys_rst), - - .x (reg_x), - .y (reg_y), - .z (reg_z), - - .ctl (reg_ctl), - .sts (reg_sts) - ); - + .cs(sys_eim_rd | sys_eim_wr), + .we(sys_eim_wr), + .address(sys_eim_addr[7 : 0]), + .write_data(write_data), + .read_data(read_data), + .error() + ); endmodule |