Updates from Pavel with new mux.

1. EIM arbiter was updated to take advantage of 3 additional address
lines, that bunnie routed from the CPU to the FPGA. Now we have 19 address
lines instead of 16, that means 19-2=17 effective bits when using 32-bit
access.

2. In the doc directory there's a draft version of current EIM memory map.

3. I've figured out why you guys could not use read and write signals from
the arbiter the way they were supposed to be used. I was wrong when I
expected Joachim's cores to have registered outputs. They have a
combinatorial output in fact. EIM arbiter's minimum latency is 1 cycle, so
we have to register data coming out of cores. I've added these three lines
to every core wrapper (sha1.v, sha256.v and sha512.v):
  reg [31 : 0]   tmp_read_data_reg;
  always @(posedge clk) tmp_read_data_reg <= tmp_read_data;
  assign read_data = tmp_read_data_reg;

4. Joachim told me, that we are going to have different types of cores
(HASH, RNG, CIPHER and so on), so I redesigned EIM multiplexor to have
separate modules for every core type. RNG and CIPHER selectors right now
are just templates with some dummy registers. Here is what was modified in
the HASH multiplexor:

4a. Core number 0 was added. It is not an actual HASH core, but a set of
global (board-level) registers. I've added three registers so far: board
type, bitstream version and one writeable dummy general-purpose register.

4b. Core instantiation was made conditional to allow selecting of what
cores to actually implement. We can have a project that offers a large
number of cores, so people can disable unnecessary cores to speed up
compile time and to save some slices for something else.

4c. I have disconnected .error() output from cores. As far as I understand
it gets asserted when some non-existent register is being addressed. In
most projects that I've seen writes to empty regions of memory are
discarded and reads return zeroes. If you really need this kind of error
checking, please re-connect this output as needed.

4d. core_selector.v has an instruction on how to add new HASH cores to our
design.

5. TC11() was added to hash_tester.c to check that we can read global
board-level registers and that we have access to segments other than
HASH. The last check reads dummy registers from RNG and CIPHER segments
(which are just templates now), this effectively tests the 3 new added
address bits.

1 files changed, 54 insertions, 4 deletions

diff --git a/sw/test-sha256/hash_tester.c b/sw/test-sha256/hash_tester.c
index 978cb82..4fbeaa3 100644
--- a/sw/test-sha256/hash_tester.c
+++ b/sw/test-sha256/hash_tester.c
@@ -62,6 +62,16 @@ int debug = 0;
 int quiet = 0;
 int repeat = 0;
 
+/* instead of core number 0 we have a page of global registers */
+#define ADDR_GLOBAL_BOARD_TYPE		EIM_BASE_ADDR + (0x00 << 2)
+#define ADDR_GLOBAL_BITSTREAM_VER	EIM_BASE_ADDR + (0x01 << 2)
+#define ADDR_GLOBAL_DUMMY_REG		EIM_BASE_ADDR + (0xFF << 2)
+
+#define SEGMENT_OFFSET_HASHES	EIM_BASE_ADDR + 0x000000
+#define SEGMENT_OFFSET_RNGS		EIM_BASE_ADDR + 0x010000
+#define SEGMENT_OFFSET_CIPHERS	EIM_BASE_ADDR + 0x020000
+
+
 /* addresses and codes common to all hash cores */
 #define ADDR_NAME0              0x00
 #define ADDR_NAME1              0x04
@@ -75,8 +85,10 @@ int repeat = 0;
 #define ADDR_BLOCK              0x40
 #define ADDR_DIGEST             0x80
 
+#define HASH_CORE_SIZE			0x400
+
 /* addresses and codes for the specific hash cores */
-#define SHA1_ADDR_BASE          EIM_BASE_ADDR  + 0x1000
+#define SHA1_ADDR_BASE          EIM_BASE_ADDR  + (1*HASH_CORE_SIZE)
 #define SHA1_ADDR_NAME0         SHA1_ADDR_BASE + ADDR_NAME0
 #define SHA1_ADDR_NAME1         SHA1_ADDR_BASE + ADDR_NAME1
 #define SHA1_ADDR_VERSION       SHA1_ADDR_BASE + ADDR_VERSION
@@ -87,7 +99,7 @@ int repeat = 0;
 #define SHA1_BLOCK_LEN          512 / 8
 #define SHA1_DIGEST_LEN         160 / 8
 
-#define SHA256_ADDR_BASE	EIM_BASE_ADDR    + 0x2000
+#define SHA256_ADDR_BASE		EIM_BASE_ADDR    + (2*HASH_CORE_SIZE)
 #define SHA256_ADDR_NAME0       SHA256_ADDR_BASE + ADDR_NAME0
 #define SHA256_ADDR_NAME1       SHA256_ADDR_BASE + ADDR_NAME1
 #define SHA256_ADDR_VERSION     SHA256_ADDR_BASE + ADDR_VERSION
@@ -98,7 +110,7 @@ int repeat = 0;
 #define SHA256_BLOCK_LEN        512 / 8
 #define SHA256_DIGEST_LEN       256 / 8
 
-#define SHA512_ADDR_BASE        EIM_BASE_ADDR    + 0x3000
+#define SHA512_ADDR_BASE        EIM_BASE_ADDR    + (3*HASH_CORE_SIZE)
 #define SHA512_ADDR_NAME0       SHA512_ADDR_BASE + ADDR_NAME0
 #define SHA512_ADDR_NAME1       SHA512_ADDR_BASE + ADDR_NAME1
 #define SHA512_ADDR_VERSION     SHA512_ADDR_BASE + ADDR_VERSION
@@ -696,6 +708,44 @@ int TC10()
     return 0;
 }
 
+int TC11()
+{
+	uint8_t board_type[4]   	= { 'P', 'V', 'T', '1'};		/* "PVT1" */
+    uint8_t bitstream_ver[4]	= { 0x00, 0x01, 0x00, 0x0B };	/* v0.1.0b */
+	uint8_t t[4];
+	
+	uint8_t seg_rngs_reg_first[4]   = { 0xAA, 0xAA, 0xAA, 0xAA};
+	uint8_t seg_rngs_reg_second[4]	= { 0xBB, 0xBB, 0xBB, 0xBB};
+	uint8_t seg_rngs_reg_third[4]   = { 0xCC, 0xCC, 0xCC, 0xCC};
+
+	uint8_t seg_ciphers_reg_first[4]	= { 0xDD, 0xDD, 0xDD, 0xDD};
+	uint8_t seg_ciphers_reg_second[4]	= { 0xEE, 0xEE, 0xEE, 0xEE};
+	uint8_t seg_ciphers_reg_third[4]	= { 0xFF, 0xFF, 0xFF, 0xFF};
+	
+		// write current time into dummy register, then try to read it back
+		// to make sure that we can actually write something into eim
+	(void)time((time_t *)t);
+	tc_write(ADDR_GLOBAL_DUMMY_REG, (void *)&t, 4);
+	
+    if (!quiet)
+		printf("TC11: Reading board type, bitstream version and dummy register from global registers.\n");
+    if (!quiet)
+		printf("TC11: Reading dummy registers from RNG and CIPHER memory segments.\n");		
+		
+    return
+        tc_expected(ADDR_GLOBAL_BOARD_TYPE,    board_type,    4) ||
+        tc_expected(ADDR_GLOBAL_BITSTREAM_VER, bitstream_ver, 4) || 
+		tc_expected(ADDR_GLOBAL_DUMMY_REG,     (void *)t,     4) ||
+		
+		tc_expected(SEGMENT_OFFSET_RNGS + (0 << 2), seg_rngs_reg_first,  4) ||
+		tc_expected(SEGMENT_OFFSET_RNGS + (1 << 2), seg_rngs_reg_second, 4) ||
+		tc_expected(SEGMENT_OFFSET_RNGS + (2 << 2), seg_rngs_reg_third,  4) ||
+		
+		tc_expected(SEGMENT_OFFSET_CIPHERS + (0 << 2), seg_ciphers_reg_first,  4) ||
+		tc_expected(SEGMENT_OFFSET_CIPHERS + (1 << 2), seg_ciphers_reg_second, 4) ||
+		tc_expected(SEGMENT_OFFSET_CIPHERS + (2 << 2), seg_ciphers_reg_third,  4);
+}
+
 /* ---------------- main ---------------- */
 
 unsigned long iter = 0;
@@ -718,7 +768,7 @@ int main(int argc, char *argv[])
     tcfp sha1_tests[] = { TC1, TC2, TC3 };
     tcfp sha256_tests[] = { TC4, TC5, TC6, TC7 };
     tcfp sha512_tests[] = { TC8, TC9, TC10 };
-    tcfp all_tests[] = { TC1, TC2, TC3, TC4, TC5, TC6, TC7, TC8, TC9, TC10 };
+    tcfp all_tests[] = { TC1, TC2, TC3, TC4, TC5, TC6, TC7, TC8, TC9, TC10, TC11 };
 
     char *usage = "Usage: %s [-h] [-d] [-q] [-r] tc...\n";
     int i, j, opt;