diff options
| author | Paul Selkirk <paul@psgd.org> | 2015-02-10 12:03:47 -0500 |
|---|---|---|
| committer | Paul Selkirk <paul@psgd.org> | 2015-02-10 12:03:47 -0500 |
| commit | 560ebacb0c576b92d7b64d728423683ad974885e (patch) | |
| tree | 20e7922961a6d28d85ebdfe51dc76e391bc18e2c /rtl/src | |
| parent | 13b8166c8989b5e83b0c998279c60c17bf46e890 (diff) | |
Updates from Pavel with new mux.
1. EIM arbiter was updated to take advantage of 3 additional address
lines, that bunnie routed from the CPU to the FPGA. Now we have 19 address
lines instead of 16, that means 19-2=17 effective bits when using 32-bit
access.
2. In the doc directory there's a draft version of current EIM memory map.
3. I've figured out why you guys could not use read and write signals from
the arbiter the way they were supposed to be used. I was wrong when I
expected Joachim's cores to have registered outputs. They have a
combinatorial output in fact. EIM arbiter's minimum latency is 1 cycle, so
we have to register data coming out of cores. I've added these three lines
to every core wrapper (sha1.v, sha256.v and sha512.v):
reg [31 : 0] tmp_read_data_reg;
always @(posedge clk) tmp_read_data_reg <= tmp_read_data;
assign read_data = tmp_read_data_reg;
4. Joachim told me, that we are going to have different types of cores
(HASH, RNG, CIPHER and so on), so I redesigned EIM multiplexor to have
separate modules for every core type. RNG and CIPHER selectors right now
are just templates with some dummy registers. Here is what was modified in
the HASH multiplexor:
4a. Core number 0 was added. It is not an actual HASH core, but a set of
global (board-level) registers. I've added three registers so far: board
type, bitstream version and one writeable dummy general-purpose register.
4b. Core instantiation was made conditional to allow selecting of what
cores to actually implement. We can have a project that offers a large
number of cores, so people can disable unnecessary cores to speed up
compile time and to save some slices for something else.
4c. I have disconnected .error() output from cores. As far as I understand
it gets asserted when some non-existent register is being addressed. In
most projects that I've seen writes to empty regions of memory are
discarded and reads return zeroes. If you really need this kind of error
checking, please re-connect this output as needed.
4d. core_selector.v has an instruction on how to add new HASH cores to our
design.
5. TC11() was added to hash_tester.c to check that we can read global
board-level registers and that we have access to segments other than
HASH. The last check reads dummy registers from RNG and CIPHER segments
(which are just templates now), this effectively tests the 3 new added
address bits.
Diffstat (limited to 'rtl/src')
| -rw-r--r-- | rtl/src/ipcore/_xmsgs/pn_parser.xmsgs | 2 | ||||
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm.gise | 2 | ||||
| -rw-r--r-- | rtl/src/ipcore/clkmgr_dcm.xise | 343 | ||||
| -rw-r--r-- | rtl/src/testbench/tb_demo_adder.v | 22 | ||||
| -rw-r--r-- | rtl/src/ucf/novena_baseline.ucf | 18 | ||||
| -rw-r--r-- | rtl/src/verilog/cipher_selector.v | 115 | ||||
| -rw-r--r-- | rtl/src/verilog/core_selector.v | 365 | ||||
| -rw-r--r-- | rtl/src/verilog/eim_arbiter.v | 20 | ||||
| -rw-r--r-- | rtl/src/verilog/eim_arbiter_cdc.v | 28 | ||||
| -rw-r--r-- | rtl/src/verilog/eim_memory.v | 182 | ||||
| -rw-r--r-- | rtl/src/verilog/novena_baseline_top.v | 40 | ||||
| -rw-r--r-- | rtl/src/verilog/novena_regs.v | 80 | ||||
| -rw-r--r-- | rtl/src/verilog/rng_selector.v | 114 |
13 files changed, 772 insertions, 559 deletions
diff --git a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs index 8fe7625..04083bd 100644 --- a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs +++ b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs @@ -8,7 +8,7 @@ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
-<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "Z:/Sandbox/external/cryptech/test/novena_base/rtl/src/ipcore/tmp/_cg/clkmgr_dcm.v" into library work</arg>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "E:/__DNSSEC/novena_base/rtl/src/ipcore/clkmgr_dcm.v" into library work</arg>
</msg>
</messages>
diff --git a/rtl/src/ipcore/clkmgr_dcm.gise b/rtl/src/ipcore/clkmgr_dcm.gise index ed6d0f7..31ed488 100644 --- a/rtl/src/ipcore/clkmgr_dcm.gise +++ b/rtl/src/ipcore/clkmgr_dcm.gise @@ -15,7 +15,7 @@ <!-- -->
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
diff --git a/rtl/src/ipcore/clkmgr_dcm.xise b/rtl/src/ipcore/clkmgr_dcm.xise index e6b0f8a..a0ba9da 100644 --- a/rtl/src/ipcore/clkmgr_dcm.xise +++ b/rtl/src/ipcore/clkmgr_dcm.xise @@ -9,18 +9,18 @@ <!-- along with the project source files, is sufficient to open and --> <!-- implement in ISE Project Navigator. --> <!-- --> - <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> + <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> </header> - <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/> + <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/> <files> <file xil_pn:name="clkmgr_dcm.ucf" xil_pn:type="FILE_UCF"> - <association xil_pn:name="Implementation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="clkmgr_dcm.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> - <association xil_pn:name="Implementation" xil_pn:seqID="3"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/> @@ -28,357 +28,28 @@ </files> <properties> - <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> - <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> - <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/> - <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/> - <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> - <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> - <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> - <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> - <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> - <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> - <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/> - <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> - <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/> - <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/> - <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/> - <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/> - <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> - <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/> - <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/> - <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/> - <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/> - <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> - <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/> <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> - <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/> - <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> - <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/> - <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/> - <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> - <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/> - <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> - <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/> - 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<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/> - <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/> - <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/> - <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> - <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> - <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/> - <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> - <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> - <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> - <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> - <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/> - <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/> - <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> - <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> - <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/> - <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/> - <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/> - <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> - <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> - <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/> - <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> - <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/> - <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/> - <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/> - <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> - <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/> - <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/> - <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> - <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Output File Name" xil_pn:value="clkmgr_dcm" xil_pn:valueState="default"/> - <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> - <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/> - <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> - <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> - <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> - <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> - <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> - <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="clkmgr_dcm_map.v" xil_pn:valueState="default"/> - <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="clkmgr_dcm_timesim.v" xil_pn:valueState="default"/> - <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="clkmgr_dcm_synthesis.v" xil_pn:valueState="default"/> - <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="clkmgr_dcm_translate.v" xil_pn:valueState="default"/> - <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> - <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/> - <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> - <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> - <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> - <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> - <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/> - <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> - <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> - <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/> - <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/> - <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/> - <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> - <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> - <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> - <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> - <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> - <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> - <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> - <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> - <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/> - <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/> - <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/> - <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> - <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> - <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> - <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/> - <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> - <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> - <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/> - <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/> - <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> - <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> - <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> - <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> - <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> - <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> - <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> - <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> - <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> - <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> - <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/> - <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/> - <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> - <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> - <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> - <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> - <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> - <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> - <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> - <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/> - <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/> - <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> - <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> - <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/> - <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> - <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> - <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/> - <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> - <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> - <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> - <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/> - <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> - <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/> - <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> - <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/> - <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/> - <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> - <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/> - <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> <!-- --> <!-- The following properties are for internal use only. These should not be modified.--> <!-- --> - <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="clkmgr_dcm" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> - <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> - <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-02-01T08:50:04" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="67BEB73269CA45ADBC7997434CEC13CB" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> diff --git a/rtl/src/testbench/tb_demo_adder.v b/rtl/src/testbench/tb_demo_adder.v index 5abbf06..76771a5 100644 --- a/rtl/src/testbench/tb_demo_adder.v +++ b/rtl/src/testbench/tb_demo_adder.v @@ -24,6 +24,7 @@ module tb_demo_adder; wire [15: 0] eim_da;
reg [15: 0] eim_da_out;
reg eim_da_drive;
+ reg [18:16] eim_a;
reg eim_oe_n;
reg eim_wr_n;
wire eim_wait_n;
@@ -41,6 +42,7 @@ module tb_demo_adder; .eim_bclk (eim_bclk),
.eim_cs0_n (eim_cs_n),
.eim_da (eim_da),
+ .eim_a (eim_a),
.eim_lba_n (eim_lba_n),
.eim_wr_n (eim_wr_n),
.eim_oe_n (eim_oe_n),
@@ -66,6 +68,7 @@ module tb_demo_adder; eim_lba_n = 1'b1;
eim_da_out = {16{1'bX}};
eim_da_drive = 1'b1;
+ eim_a = 3'bXXX;
eim_oe_n = 1'b1;
eim_wr_n = 1'b1;
end
@@ -81,6 +84,11 @@ module tb_demo_adder; //
#2000;
//
+ eim_read(19'h10000, eim_rd); // read Z <-- should be 0xBB77B7B7
+ //
+ #10000;
+ //
+ /*
eim_write({12'h321, 2'd0, 2'b00}, 32'hAA_55_A5_A5); // write X
#100;
eim_write({12'h321, 2'd1, 2'b00}, 32'h11_22_12_12); // write Y
@@ -93,6 +101,7 @@ module tb_demo_adder; eim_read( {12'h321, 2'd3, 2'b00}, eim_rd); // read {STS, CTL} <-- should be 0x0001_0001
#100;
eim_read( {12'h321, 2'd2, 2'b00}, eim_rd); // read Z <-- should be 0xBB77B7B7
+ */
end
//
@@ -100,17 +109,19 @@ module tb_demo_adder; //
integer wr;
task eim_write;
- input [15: 0] addr;
+ input [18: 0] addr;
input [31: 0] data;
begin
#15 eim_cs_n = 1'b0;
eim_lba_n = 1'b0;
- eim_da_out = addr;
+ eim_da_out = addr[15: 0];
+ eim_a = addr[18:16];
eim_wr_n = 1'b0;
#15 eim_bclk = 1'b1;
#15 eim_bclk = 1'b0;
eim_lba_n = 1'b1;
eim_da_out = data[15:0];
+ eim_a = 3'bXXX;
#15 eim_bclk = 1'b1;
#15 eim_bclk = 1'b0;
eim_da_out = data[31:16];
@@ -132,19 +143,20 @@ module tb_demo_adder; // Read Access
//
task eim_read;
- input [15: 0] addr;
+ input [18: 0] addr;
output [31: 0] data;
begin
#15 eim_cs_n = 1'b0;
eim_lba_n = 1'b0;
- eim_da_out = addr;
-
+ eim_da_out = addr[15: 0];
+ eim_a = addr[18:16];
#15 eim_bclk = 1'b1;
#15 eim_bclk = 1'b0;
eim_lba_n = 1'b1;
eim_oe_n = 1'b0;
eim_da_drive = 1'b0;
+ eim_a = 3'bXXX;
#15;
while (eim_wait_n == 1'b0) begin
eim_bclk = 1'b1;
diff --git a/rtl/src/ucf/novena_baseline.ucf b/rtl/src/ucf/novena_baseline.ucf index 7902eb7..cc937f8 100644 --- a/rtl/src/ucf/novena_baseline.ucf +++ b/rtl/src/ucf/novena_baseline.ucf @@ -85,12 +85,26 @@ NET "eim_da<12>" LOC = "C7" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | D NET "eim_da<13>" LOC = "C11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ; NET "eim_da<14>" LOC = "C4" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ; NET "eim_da<15>" LOC = "B6" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ; +
+NET "eim_a<16>" LOC = "A11" | IOSTANDARD = "LVCMOS33" ; +NET "eim_a<17>" LOC = "B12" | IOSTANDARD = "LVCMOS33" ; +NET "eim_a<18>" LOC = "D14" | IOSTANDARD = "LVCMOS33" ;
NET "eim_lba_n" LOC = "B14" | IOSTANDARD = "LVCMOS33" ; NET "eim_wr_n" LOC = "C14" | IOSTANDARD = "LVCMOS33" ; NET "eim_oe_n" LOC = "C10" | IOSTANDARD = "LVCMOS33" ; -NET "eim_wait_n" LOC = "A7" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ; - +NET "eim_wait_n" LOC = "A7" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 12 ;
+ +NET "ct_led<0>" LOC = K6 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "ct_led<1>" LOC = H4 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "ct_led<2>" LOC = H3 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "ct_led<3>" LOC = M1 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "ct_led<4>" LOC = L7 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "ct_led<5>" LOC = G1 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "ct_led<6>" LOC = T2 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; +NET "ct_led<7>" LOC = H7 | IOSTANDARD = LVCMOS33 | SLEW = SLOW ; + +NET "ct_noise" LOC = L4 | IOSTANDARD = LVCMOS33 ; #------------------------------------------------------------------------------- # EIM Input Timing diff --git a/rtl/src/verilog/cipher_selector.v b/rtl/src/verilog/cipher_selector.v new file mode 100644 index 0000000..31dfe4b --- /dev/null +++ b/rtl/src/verilog/cipher_selector.v @@ -0,0 +1,115 @@ +//====================================================================== +// +// cipher_selector.v +// ----------------- +// Top level wrapper that creates the Cryptech coretest system. +// The wrapper contains instances of external interface, coretest +// and the core to be tested. And if more than one core is +// present the wrapper also includes address and data muxes. +// +// +// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov +// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module cipher_selector + ( + input wire sys_clk, + input wire sys_rst,
+ input wire sys_ena, + + input wire [13: 0] sys_eim_addr, + input wire sys_eim_wr, + input wire sys_eim_rd, + output wire [31 : 0] sys_read_data, + input wire [31 : 0] sys_write_data + ); +
+
+ //
+ // Output Register
+ //
+ reg [31: 0] tmp_read_data;
+ assign sys_read_data = tmp_read_data;
+
+
+ /* So far we have no CIPHER cores, let's make some dummy 32-bit registers here
+ * to prevent ISE from complaining that we don't use input ports.
+ */
+
+ reg [31: 0] reg_dummy_first;
+ reg [31: 0] reg_dummy_second;
+ reg [31: 0] reg_dummy_third;
+
+ always @(posedge sys_clk) + // + if (sys_rst) begin
+ reg_dummy_first <= {8{4'hD}};
+ reg_dummy_second <= {8{4'hE}};
+ reg_dummy_third <= {8{4'hF}}; + end else if (sys_ena) begin
+ //
+ if (sys_eim_wr) begin
+ //
+ // WRITE handler
+ //
+ case (sys_eim_addr)
+ 14'd0: reg_dummy_first <= sys_write_data;
+ 14'd1: reg_dummy_second <= sys_write_data;
+ 14'd2: reg_dummy_third <= sys_write_data;
+ endcase
+ //
+ end
+ //
+ if (sys_eim_rd) begin
+ //
+ // READ handler
+ //
+ case (sys_eim_addr)
+ 14'd0: tmp_read_data <= reg_dummy_first;
+ 14'd1: tmp_read_data <= reg_dummy_second;
+ 14'd2: tmp_read_data <= reg_dummy_third; + //
+ default: tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
+ /* + default: tmp_read_data <= {32{1'bX}}; // don't care what to read from non-existent locations
+ */
+ endcase
+ //
+ end
+ //
+ end + + +endmodule + +//====================================================================== +// EOF core_selector.v +//====================================================================== diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 7479848..e39a8b1 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -1,6 +1,6 @@ //====================================================================== // -// coretest_hashes.v +// core_selector.v // ----------------- // Top level wrapper that creates the Cryptech coretest system. // The wrapper contains instances of external interface, coretest @@ -42,182 +42,203 @@ module core_selector ( input wire sys_clk, - input wire sys_rst, + input wire sys_rst,
+ input wire sys_ena, input wire [13: 0] sys_eim_addr, input wire sys_eim_wr, input wire sys_eim_rd, - output wire [31 : 0] read_data, - input wire [31 : 0] write_data + output wire [31 : 0] sys_read_data, + input wire [31 : 0] sys_write_data ); - - - //---------------------------------------------------------------- - // Internal constant and parameter definitions. - //---------------------------------------------------------------- - parameter SHA1_ADDR_PREFIX = 6'b000100; // 0x1000 - 0x13ff - parameter SHA256_ADDR_PREFIX = 6'b001000; // 0x2000 - 0x23ff - parameter SHA512_ADDR_PREFIX = 6'b001100; // 0x3000 - 0x33ff - - - //---------------------------------------------------------------- - // Wires and registers - //---------------------------------------------------------------- - wire clk = sys_clk; - wire reset_n = !sys_rst; - wire [13:0] address = sys_eim_addr; - wire cs = sys_eim_wr | sys_eim_rd; - wire we = sys_eim_wr; - - reg [31:0] read_reg; - reg error_reg; - - // sha1 connections. - reg sha1_cs; - reg sha1_we; - reg [7:0] sha1_address; - reg [31:0] sha1_write_data; - wire [31:0] sha1_read_data; - wire sha1_error; - - // sha256 connections. - reg sha256_cs; - reg sha256_we; - reg [7:0] sha256_address; - reg [31:0] sha256_write_data; - wire [31:0] sha256_read_data; - wire sha256_error; - - // sha512 connections. - reg sha512_cs; - reg sha512_we; - reg [7:0] sha512_address; - reg [31:0] sha512_write_data; - wire [31:0] sha512_read_data; - wire sha512_error; - - - //---------------------------------------------------------------- - // Concurrent assignment. - //---------------------------------------------------------------- - assign read_data = read_reg; - - //---------------------------------------------------------------- - // Core instantiations. - //---------------------------------------------------------------- - sha1 sha1( - // Clock and reset. - .clk(clk), - .reset_n(reset_n), - - // Control. - .cs(sha1_cs), - .we(sha1_we), - - // Data ports. - .address(sha1_address), - .write_data(sha1_write_data), - .read_data(sha1_read_data), - .error(sha1_error) - ); - - - sha256 sha256( - // Clock and reset. - .clk(clk), - .reset_n(reset_n), - - // Control. - .cs(sha256_cs), - .we(sha256_we), - - // Data ports. - .address(sha256_address), - .write_data(sha256_write_data), - .read_data(sha256_read_data), - .error(sha256_error) - ); - - - sha512 sha512( - // Clock and reset. - .clk(clk), - .reset_n(reset_n), - - // Control. - .cs(sha512_cs), - .we(sha512_we), - - // Data ports. - .address(sha512_address), - .write_data(sha512_write_data), - .read_data(sha512_read_data), - .error(sha512_error) - ); - - //---------------------------------------------------------------- - // address_mux - // - // Combinational data mux that handles addressing between - // cores using the 32-bit memory like interface. - //---------------------------------------------------------------- - always @* - begin : address_mux - // Default assignments. - sha1_cs = 0; - sha1_we = 0; - sha1_address = 8'h00; - sha1_write_data = 32'h00000000; - - sha256_cs = 0; - sha256_we = 0; - sha256_address = 8'h00; - sha256_write_data = 32'h00000000; - - sha512_cs = 0; - sha512_we = 0; - sha512_address = 8'h00; - sha512_write_data = 32'h00000000; - - // address mux - case (address[13:8]) - SHA1_ADDR_PREFIX: - begin - sha1_cs = 1; - sha1_we = we; - sha1_address = address[7:0]; - sha1_write_data = write_data; - read_reg = sha1_read_data; - error_reg = sha1_error; - end - - SHA256_ADDR_PREFIX: - begin - sha256_cs = 1; - sha256_we = we; - sha256_address = address[7:0]; - sha256_write_data = write_data; - read_reg = sha256_read_data; - error_reg = sha256_error; - end - - SHA512_ADDR_PREFIX: - begin - sha512_cs = 1; - sha512_we = we; - sha512_address = address[7:0]; - sha512_write_data = write_data; - read_reg = sha512_read_data; - error_reg = sha512_error; - end - - default: - begin - read_reg = 32'hZZZZ; - end - endcase - - end // address_mux +
+
+ /* In this memory segment (HASHES) we have 14 address bits. Every core has 8-bit internal address space,
+ * so we can have up to 2^(14-8) = 64 cores here.
+ *
+ * Core #0 is not an actual HASH core, but a set of board-level (global) registers, that can be used to
+ * get information about hardware (board type, bitstream version and so on).
+ *
+ * So far we have three cores: SHA-1, SHA-256 and SHA-512.
+ */
+
+ /*********************************************************
+ * To add new HASH core named XXX follow the steps below *
+ *********************************************************
+ *
+ * 1. Add corresponding `define under "List of Available Cores", this will allow users to exclude your
+ * core from implementation to save some slices in case they don't need it.
+ *
+ * `define USE_CORE_XXX
+ *
+ *
+ * 2. Choose address of your new core and add corresponding line under "Core Address Table". Core addresses
+ * can be in the range from 1 to 63 inclusively. Core address 0 is reserved for a page of global registers
+ * and must not be used.
+ *
+ * localparam CORE_ADDR_XXX = 6'dN;
+ *
+ *
+ * 3. Add instantiation of your new core after all existing cores surrounded by conditional synthesis directives.
+ * You also need a 32-bit output (read data) bus for your core and an enable flag. Note that sys_rst in
+ * an active-high sync reset signal.
+ *
+ * `ifdef USE_CORE_XXX
+ * wire [31: 0] read_data_xxx;
+ * wire enable_xxx = sys_ena && (addr_core_num == CORE_ADDR_XXX);
+ * xxx xxx_inst + * ( + * .clk(sys_clk), + * .reset_n(~sys_rst), + * .cs(enable_xxx & (sys_eim_rd | sys_eim_wr)), + * .we(sys_eim_wr), + * .address(addr_core_reg), + * .write_data(sys_write_data), + * .read_data(read_data_xxx), + * .error() + * );
+ * `endif
+ *
+ *
+ * 4. Add previously created data bus to "Output (Read Data) Multiplexor" in the end of this file.
+ *
+ * `ifdef USE_CORE_XXX CORE_ADDR_XXX: sys_read_data_mux = read_data_xxx; `endif
+ *
+ */
+
+
+ //----------------------------------------------------------------
+ // Address Decoder
+ //----------------------------------------------------------------
+ wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; // upper 6 bits specify core being addressed
+ wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; // lower 8 bits specify register offset in core
+
+
+ /* We can comment following lines to exclude cores from implementation
+ * in case we run out of slices.
+ */
+
+ //----------------------------------------------------------------
+ // List of Available Cores
+ //----------------------------------------------------------------
+ `define USE_CORE_SHA1
+ `define USE_CORE_SHA256
+ `define USE_CORE_SHA512
+
+
+ //----------------------------------------------------------------
+ // Core Address Table
+ //----------------------------------------------------------------
+ localparam CORE_ADDR_GLOBAL_REGS = 6'd0;
+ localparam CORE_ADDR_SHA1 = 6'd1;
+ localparam CORE_ADDR_SHA256 = 6'd2;
+ localparam CORE_ADDR_SHA512 = 6'd3;
+
+
+ //----------------------------------------------------------------
+ // Global Registers
+ //---------------------------------------------------------------- + wire [31: 0] read_data_global;
+ wire enable_global = sys_ena && (addr_core_num == CORE_ADDR_GLOBAL_REGS);
+ novena_regs novena_regs_inst + ( + .clk(sys_clk), + .rst(sys_rst), + + .cs(enable_global & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_global)
+ );
+
+
+ //----------------------------------------------------------------
+ // SHA-1
+ //----------------------------------------------------------------
+ `ifdef USE_CORE_SHA1
+ wire [31: 0] read_data_sha1;
+ wire enable_sha1 = sys_ena && (addr_core_num == CORE_ADDR_SHA1);
+ sha1 sha1_inst + ( + .clk(sys_clk), + .reset_n(~sys_rst), + + .cs(enable_sha1 & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_sha1), + .error() + );
+ `endif
+
+
+ //----------------------------------------------------------------
+ // SHA-256
+ //----------------------------------------------------------------
+ `ifdef USE_CORE_SHA256
+ wire [31: 0] read_data_sha256;
+ wire enable_sha256 = sys_ena && (addr_core_num == CORE_ADDR_SHA256);
+ sha256 sha256_inst + ( + .clk(sys_clk), + .reset_n(~sys_rst), + + .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_sha256), + .error() + );
+ `endif
+
+
+ //----------------------------------------------------------------
+ // SHA-512
+ //----------------------------------------------------------------
+ `ifdef USE_CORE_SHA512
+ wire [31: 0] read_data_sha512;
+ wire enable_sha512 = sys_ena && (addr_core_num == CORE_ADDR_SHA512);
+ sha512 sha512_inst + ( + .clk(sys_clk), + .reset_n(~sys_rst), + + .cs(enable_sha512 & (sys_eim_rd | sys_eim_wr)), + .we(sys_eim_wr), + + .address(addr_core_reg), + .write_data(sys_write_data), + .read_data(read_data_sha512), + .error() + );
+ `endif
+
+
+ //----------------------------------------------------------------
+ // Output (Read Data) Multiplexor
+ //----------------------------------------------------------------
+ reg [31: 0] sys_read_data_mux;
+ assign sys_read_data = sys_read_data_mux;
+
+ always @*
+ // + case (addr_core_num)
+ //
+ CORE_ADDR_GLOBAL_REGS: sys_read_data_mux = read_data_global;
+ `ifdef USE_CORE_SHA1 CORE_ADDR_SHA1: sys_read_data_mux = read_data_sha1; `endif
+ `ifdef USE_CORE_SHA256 CORE_ADDR_SHA256: sys_read_data_mux = read_data_sha256; `endif
+ `ifdef USE_CORE_SHA512 CORE_ADDR_SHA512: sys_read_data_mux = read_data_sha512; `endif
+ //
+ default: sys_read_data_mux = {32{1'b0}};
+ // + endcase
+
endmodule diff --git a/rtl/src/verilog/eim_arbiter.v b/rtl/src/verilog/eim_arbiter.v index 3dc6260..d21799f 100644 --- a/rtl/src/verilog/eim_arbiter.v +++ b/rtl/src/verilog/eim_arbiter.v @@ -39,7 +39,7 @@ module eim_arbiter ( - eim_bclk, eim_cs0_n, eim_da, + eim_bclk, eim_cs0_n, eim_da, eim_a, eim_lba_n, eim_wr_n, eim_oe_n, eim_wait_n, @@ -55,7 +55,8 @@ module eim_arbiter // input wire eim_bclk; // | eim bus input wire eim_cs0_n; // | - inout wire [15: 0] eim_da; // | + inout wire [15: 0] eim_da; // |
+ input wire [18:16] eim_a; // | input wire eim_lba_n; // | input wire eim_wr_n; // | input wire eim_oe_n; // | @@ -63,7 +64,7 @@ module eim_arbiter input wire sys_clk; // system clock - output wire [13: 0] sys_addr; // | user bus + output wire [16: 0] sys_addr; // | user bus output wire sys_wren; // | output wire [31: 0] sys_data_out; // | output wire sys_rden; // | @@ -107,7 +108,7 @@ module eim_arbiter localparam EIM_FSM_STATE_READ_DONE = 5'b1_0_111; // transaction complete reg [ 4: 0] eim_fsm_state = EIM_FSM_STATE_INIT; // fsm state - reg [13: 0] eim_addr_latch = {14{1'bX}}; // transaction address + reg [16: 0] eim_addr_latch = {17{1'bX}}; // transaction address reg [15: 0] eim_write_lsb_latch = {16{1'bX}}; // lower 16 bits of data to write /* These flags are used to wake up from INIT state. */ @@ -183,7 +184,7 @@ module eim_arbiter always @(posedge eim_bclk) // if ((eim_fsm_state == EIM_FSM_STATE_INIT) && (eim_write_start_flag || eim_read_start_flag)) - eim_addr_latch <= da_ro[15:2]; + eim_addr_latch <= {eim_a[18:16], da_ro[15:2]}; // @@ -256,10 +257,11 @@ module eim_arbiter // /* This block is used to transfer request data from BCLK clock domain to SYS_CLK clock domain and - * then transfer acknowledge from SYS_CLK to BCLK clock domain in return. Af first 1+1+14+32 = 48 bits - * are transfered, these are: write flag, read flag, address, write data. During read transaction - * some bogus write data is passed, which is not used later anyway. During read requests 32 bits of data - * are returned, during write requests 32 bits of bogus data are returned, that are never used later. + * then transfer acknowledge from SYS_CLK to BCLK clock domain in return. Af first 1+1+3+14+32 = 51 bits + * are transfered, these are: write flag, read flag, msb part of address, lsb part of address, write data. + * During read transaction some bogus write data is passed, which is not used later anyway. During read + * requests 32 bits of data are returned, during write requests 32 bits of bogus data are returned, + * that are never used later. */ eim_arbiter_cdc eim_cdc diff --git a/rtl/src/verilog/eim_arbiter_cdc.v b/rtl/src/verilog/eim_arbiter_cdc.v index c9df62e..a0412fe 100644 --- a/rtl/src/verilog/eim_arbiter_cdc.v +++ b/rtl/src/verilog/eim_arbiter_cdc.v @@ -49,11 +49,11 @@ module eim_arbiter_cdc input wire eim_clk; // eim clock input wire eim_req; // eim transaction request output wire eim_ack; // eim transaction acknowledge - input wire [47: 0] eim_din; // data from cpu to fpga (write access) + input wire [50: 0] eim_din; // data from cpu to fpga (write access) output wire [31: 0] eim_dout; // data from fpga to cpu (read access) input wire sys_clk; // user internal clock - output wire [13: 0] sys_addr; // user access address + output wire [16: 0] sys_addr; // user access address output wire sys_wren; // user write flag output wire [31: 0] sys_data_out; // user write data output wire sys_rden; // user read flag @@ -64,11 +64,11 @@ module eim_arbiter_cdc // EIM_CLK -> SYS_CLK Request // wire sys_req; // request pulse in sys_clk clock domain - wire [47: 0] sys_dout; // transaction data in sys_clk clock domain + wire [50: 0] sys_dout; // transaction data in sys_clk clock domain cdc_bus_pulse # ( - .DATA_WIDTH (48) // {write, read, addr, data} + .DATA_WIDTH (51) // {write, read, msb addr, lsb addr, data} ) cdc_eim_sys ( @@ -85,16 +85,16 @@ module eim_arbiter_cdc // // Output Registers // - reg [13: 0] sys_addr_reg = {14{1'bX}}; // - reg sys_wren_reg = 1'b0; // + reg sys_wren_reg = 1'b0; //
+ reg sys_rden_reg = 1'b0; //
+ reg [16: 0] sys_addr_reg = {17{1'bX}}; // reg [31: 0] sys_data_out_reg = {32{1'bX}}; // - reg sys_rden_reg = 1'b0; // - +
+ assign sys_wren = sys_wren_reg;
+ assign sys_rden = sys_rden_reg; assign sys_addr = sys_addr_reg; - assign sys_wren = sys_wren_reg; assign sys_data_out = sys_data_out_reg; - assign sys_rden = sys_rden_reg; - + // // System (User) Clock Access Handler @@ -102,10 +102,10 @@ module eim_arbiter_cdc always @(posedge sys_clk) // if (sys_req) begin // request detected? - sys_wren_reg <= sys_dout[47]; // set write flag if needed - sys_addr_reg <= sys_dout[45:32]; // set operation address + sys_wren_reg <= sys_dout[50]; // set write flag if needed
+ sys_rden_reg <= sys_dout[49]; // set read flag if needed + sys_addr_reg <= sys_dout[48:32]; // set operation address sys_data_out_reg <= sys_dout[31: 0]; // set data to write - sys_rden_reg <= sys_dout[46]; // set read flag if needed end else begin // no request active sys_wren_reg <= 1'b0; // clear write flag sys_rden_reg <= 1'b0; // clear read flag diff --git a/rtl/src/verilog/eim_memory.v b/rtl/src/verilog/eim_memory.v new file mode 100644 index 0000000..5258376 --- /dev/null +++ b/rtl/src/verilog/eim_memory.v @@ -0,0 +1,182 @@ +//====================================================================== +// +// coretest_hashes.v +// ----------------- +// Top level wrapper that creates the Cryptech coretest system. +// The wrapper contains instances of external interface, coretest +// and the core to be tested. And if more than one core is +// present the wrapper also includes address and data muxes. +// +// +// Author: Pavel Shatov +// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//======================================================================
+
+module eim_memory
+ (
+ input wire sys_clk, + input wire sys_rst, + + input wire [16: 0] sys_eim_addr, + input wire sys_eim_wr, + input wire sys_eim_rd, + output wire [31: 0] sys_read_data, + input wire [31: 0] sys_write_data
+ );
+
+
+ /* Three upper bits of address [16:14] are used to select memory segment.
+ * There can be eight segments. So far segment 0 is used for hashes,
+ * segment 1 is reserved for random number generators, segment 2 is reserved
+ * for chiphers. Other segments are not used so far.
+ */
+
+ /* Every segment has its own memory map, take at look at corresponding selectors
+ * for more information.
+ */
+
+ //----------------------------------------------------------------
+ // Segment Decoder
+ //----------------------------------------------------------------
+ localparam SEGMENT_ADDR_HASHES = 3'd0;
+ localparam SEGMENT_ADDR_RNGS = 3'd1;
+ localparam SEGMENT_ADDR_CIPHERS = 3'd2;
+
+ wire [ 2: 0] addr_segment = sys_eim_addr[16:14]; // 3 upper bits are decoded here
+ wire [13: 0] addr_segment_int = sys_eim_addr[13: 0]; // 14 lower bits are decoded individually
+ // in corresponding segment selectors
+
+ wire [31: 0] segment_hashes_read_data; // data read from HASHES segment
+ wire [31: 0] segment_rngs_read_data; // data read from RNGS segment
+ wire [31: 0] segment_ciphers_read_data; // data read from CIPHERS segment
+
+ wire segment_enable_hashes = (addr_segment == SEGMENT_ADDR_HASHES) ? 1'b1 : 1'b0; // HASHES segment is being addressed
+ wire segment_enable_rngs = (addr_segment == SEGMENT_ADDR_RNGS) ? 1'b1 : 1'b0; // RNGS segment is being addressed
+ wire segment_enable_ciphers = (addr_segment == SEGMENT_ADDR_CIPHERS) ? 1'b1 : 1'b0; // CIPHERS segment is being addressed
+
+
+ //----------------------------------------------------------------
+ // Output (Read Data) Bus
+ //----------------------------------------------------------------
+ reg [31: 0] sys_read_data_reg;
+ assign sys_read_data = sys_read_data_reg;
+
+ always @*
+ //
+ case (addr_segment)
+ SEGMENT_ADDR_HASHES: sys_read_data_reg = segment_hashes_read_data;
+ SEGMENT_ADDR_RNGS: sys_read_data_reg = segment_rngs_read_data;
+ SEGMENT_ADDR_CIPHERS: sys_read_data_reg = segment_ciphers_read_data;
+ default: sys_read_data_reg = {32{1'b0}};
+ endcase
+
+
+
+ //---------------------------------------------------------------- + // HASH Core Selector + // + // This selector is used to map core registers into + // EIM address space and select which core to send EIM read and + // write operations to. + //----------------------------------------------------------------
+ core_selector segment_cores
+ (
+ .sys_clk(sys_clk), + .sys_rst(sys_rst), +
+ .sys_ena(segment_enable_hashes), // only enable active selector
+ + .sys_eim_addr(addr_segment_int), // we only connect 14 lower bits of address here,
+ // because we have already decoded 3 upper bits earlier,
+ // every segment can have its own address decoder. + .sys_eim_wr(sys_eim_wr), + .sys_eim_rd(sys_eim_rd), + + .sys_write_data(sys_write_data), + .sys_read_data(segment_hashes_read_data) // output from HASHES segment
+ );
+
+
+ //---------------------------------------------------------------- + // RNG Selector + // + // This selector is used to map random number generator registers into + // EIM address space and select which RNG to send EIM read and + // write operations to. So far there are no RNG cores. + //----------------------------------------------------------------
+ rng_selector segment_rngs
+ (
+ .sys_clk(sys_clk), + .sys_rst(sys_rst), +
+ .sys_ena(segment_enable_rngs), // only enable active selector
+ + .sys_eim_addr(addr_segment_int), // we only connect 14 lower bits of address here,
+ // because we have already decoded 3 upper bits earlier,
+ // every segment can have its own address decoder. + .sys_eim_wr(sys_eim_wr), + .sys_eim_rd(sys_eim_rd), + + .sys_write_data(sys_write_data), + .sys_read_data(segment_rngs_read_data) // output from RNGS segment
+ );
+
+
+ //---------------------------------------------------------------- + // CIPHER Selector + // + // This selector is used to map cipher registers into + // EIM address space and select which CIPHER to send EIM read and + // write operations to. So far there are no CIPHER cores. + //----------------------------------------------------------------
+ cipher_selector segment_ciphers
+ (
+ .sys_clk(sys_clk), + .sys_rst(sys_rst), +
+ .sys_ena(segment_enable_ciphers), // only enable active selector
+ + .sys_eim_addr(addr_segment_int), // we only connect 14 lower bits of address here,
+ // because we have already decoded 3 upper bits earlier,
+ // every segment can have its own address decoder. + .sys_eim_wr(sys_eim_wr), + .sys_eim_rd(sys_eim_rd), + + .sys_write_data(sys_write_data), + .sys_read_data(segment_ciphers_read_data) // output from CIPHERS segment
+ );
+
+
+endmodule
+
+
+//====================================================================== +// EOF eim_memory.v +//====================================================================== diff --git a/rtl/src/verilog/novena_baseline_top.v b/rtl/src/verilog/novena_baseline_top.v index 20bf28d..cc9e5e7 100644 --- a/rtl/src/verilog/novena_baseline_top.v +++ b/rtl/src/verilog/novena_baseline_top.v @@ -49,13 +49,14 @@ module novena_baseline_top input wire reset_mcu_b_pin, // Cryptech avalanche noise board input and LED outputs - input wire ct_avalanche_noise, - output wire [07 : 0] ct_avalanche_led, + input wire ct_noise, + output wire [07 : 0] ct_led, // EIM interface input wire eim_bclk, // EIM burst clock. Started by the CPU. input wire eim_cs0_n, // Chip select (active low). - inout wire [15 : 0] eim_da, // Bidirectional address and data port. + inout wire [15 : 0] eim_da, // Bidirectional address and data port.
+ input wire [18: 16] eim_a, // MSB part of address port. input wire eim_lba_n, // Latch address signal (active low). input wire eim_wr_n, // write enable signal (active low). input wire eim_oe_n, // output enable signal (active low). @@ -98,7 +99,7 @@ module novena_baseline_top // EIM arbiter handles EIM access and transfers it into // `sys_clk' clock domain. //---------------------------------------------------------------- - wire [13: 0] sys_eim_addr; + wire [16: 0] sys_eim_addr; wire sys_eim_wr; wire sys_eim_rd; wire [31: 0] sys_eim_dout; @@ -107,9 +108,10 @@ module novena_baseline_top eim_arbiter eim ( .eim_bclk(eim_bclk_buf), - .eim_cs0_n (eim_cs0_n), - .eim_da(eim_da), - .eim_lba_n (eim_lba_n), + .eim_cs0_n(eim_cs0_n), + .eim_da(eim_da),
+ .eim_a(eim_a), + .eim_lba_n(eim_lba_n), .eim_wr_n(eim_wr_n), .eim_oe_n(eim_oe_n), .eim_wait_n(eim_wait_n), @@ -125,24 +127,23 @@ module novena_baseline_top //---------------------------------------------------------------- - // Core Selector (MUX) + // Memory Mapper // - // This multiplexer is used to map ore registers into - // EIM address space and select which core to send EIM read and - // write operations to. - //---------------------------------------------------------------- - core_selector mux - ( - .sys_clk(sys_clk), + // This multiplexer is used to map different types of cores, such as
+ // hashes, RNGs and ciphers to different regions (segments) of memory. + //----------------------------------------------------------------
+ eim_memory mem
+ (
+ .sys_clk(sys_clk), .sys_rst(sys_rst), .sys_eim_addr(sys_eim_addr), .sys_eim_wr(sys_eim_wr), .sys_eim_rd(sys_eim_rd), - .write_data(sys_eim_dout), - .read_data(sys_eim_din) - ); + .sys_write_data(sys_eim_dout), + .sys_read_data(sys_eim_din)
+ ); //---------------------------------------------------------------- @@ -166,7 +167,7 @@ module novena_baseline_top // Logic specific to the Cryptech use of the Novena. // Currently we just hard wire the LED outputs. //---------------------------------------------------------------- - assign ct_avalanche_led = 8'h55; + assign ct_led = {8{ct_noise}}; //---------------------------------------------------------------- @@ -178,6 +179,7 @@ module novena_baseline_top // been configured. //---------------------------------------------------------------- assign apoptosis_pin = 1'b0; +
endmodule diff --git a/rtl/src/verilog/novena_regs.v b/rtl/src/verilog/novena_regs.v new file mode 100644 index 0000000..88b35ab --- /dev/null +++ b/rtl/src/verilog/novena_regs.v @@ -0,0 +1,80 @@ +`timescale 1ns / 1ps
+
+module novena_regs
+ ( + input wire clk, + input wire rst, + + input wire cs, + input wire we, + + input wire [ 7 : 0] address, + input wire [31 : 0] write_data, + output wire [31 : 0] read_data
+ );
+
+
+ //----------------------------------------------------------------
+ // Board-Level Registers
+ //----------------------------------------------------------------
+ localparam ADDR_BOARD_TYPE = 8'h00; // board id
+ localparam ADDR_FIRMWARE_VER = 8'h01; // bitstream version
+ localparam ADDR_DUMMY_REG = 8'hFF; // general-purpose register
+
+
+ //----------------------------------------------------------------
+ // Constants
+ //----------------------------------------------------------------
+ localparam NOVENA_BOARD_TYPE = 32'h50565431; // PVT1
+ localparam NOVENA_DESIGN_VER = 32'h00_01_00_0b; // v0.1.0b + + + //
+ // Output Register
+ //
+ reg [31: 0] tmp_read_data;
+ assign read_data = tmp_read_data;
+
+
+ /* This dummy register can be used by users to check that they can actually write something.
+ */
+
+ reg [31: 0] reg_dummy;
+
+
+ //
+ // Access Handler
+ //
+ always @(posedge clk) + // + if (rst) reg_dummy <= {32{1'b0}}; + else if (cs) begin
+ //
+ if (we) begin
+ //
+ // WRITE handler
+ //
+ case (address)
+ ADDR_DUMMY_REG: reg_dummy <= write_data;
+ endcase
+ //
+ end else begin
+ //
+ // READ handler
+ //
+ case (address)
+ ADDR_BOARD_TYPE: tmp_read_data <= NOVENA_BOARD_TYPE;
+ ADDR_FIRMWARE_VER: tmp_read_data <= NOVENA_DESIGN_VER;
+ ADDR_DUMMY_REG: tmp_read_data <= reg_dummy;
+ //
+ default: tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
+ /* + default: tmp_read_data <= {32{1'bX}}; // don't care what to read from non-existent locations
+ */
+ endcase
+ //
+ end
+ //
+ end +
+endmodule
diff --git a/rtl/src/verilog/rng_selector.v b/rtl/src/verilog/rng_selector.v new file mode 100644 index 0000000..7a1fe7c --- /dev/null +++ b/rtl/src/verilog/rng_selector.v @@ -0,0 +1,114 @@ +//====================================================================== +// +// rng_selector.v +// ----------------- +// Top level wrapper that creates the Cryptech coretest system. +// The wrapper contains instances of external interface, coretest +// and the core to be tested. And if more than one core is +// present the wrapper also includes address and data muxes. +// +// +// Authors: Joachim Strombergson, Paul Selkirk, Pavel Shatov +// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module rng_selector + ( + input wire sys_clk, + input wire sys_rst,
+ input wire sys_ena, + + input wire [13: 0] sys_eim_addr, + input wire sys_eim_wr, + input wire sys_eim_rd, + output wire [31 : 0] sys_read_data, + input wire [31 : 0] sys_write_data + ); +
+
+ //
+ // Output Register
+ //
+ reg [31: 0] tmp_read_data;
+ assign sys_read_data = tmp_read_data;
+
+
+ /* So far we have no RNG cores, let's make some dummy 32-bit registers here
+ * to prevent ISE from complaining that we don't use input ports.
+ */
+
+ reg [31: 0] reg_dummy_first;
+ reg [31: 0] reg_dummy_second;
+ reg [31: 0] reg_dummy_third;
+
+ always @(posedge sys_clk) + // + if (sys_rst) begin
+ reg_dummy_first <= {8{4'hA}};
+ reg_dummy_second <= {8{4'hB}};
+ reg_dummy_third <= {8{4'hC}}; + end else if (sys_ena) begin
+ //
+ if (sys_eim_wr) begin
+ //
+ // WRITE handler
+ //
+ case (sys_eim_addr)
+ 14'd0: reg_dummy_first <= sys_write_data;
+ 14'd1: reg_dummy_second <= sys_write_data;
+ 14'd2: reg_dummy_third <= sys_write_data;
+ endcase
+ //
+ end
+ //
+ if (sys_eim_rd) begin
+ //
+ // READ handler
+ //
+ case (sys_eim_addr)
+ 14'd0: tmp_read_data <= reg_dummy_first;
+ 14'd1: tmp_read_data <= reg_dummy_second;
+ 14'd2: tmp_read_data <= reg_dummy_third; + //
+ default: tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
+ /* + default: tmp_read_data <= {32{1'bX}}; // don't care what to read from non-existent locations
+ */
+ endcase
+ //
+ end
+ //
+ end + +endmodule + +//====================================================================== +// EOF core_selector.v +//====================================================================== |