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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2015-02-02 20:54:59 +0100 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2015-02-02 20:54:59 +0100 |
| commit | f1fe0708e988356413f3160c6a85dc8d82eba3a0 (patch) | |
| tree | 6b15f41c47bce99f665430fb7967dd5b9e931bbb /rtl/src/verilog | |
| parent | 86311d72381423582f2de5f91fa9fbb447098934 (diff) | |
Added real prefix detection of sha255 core.
Diffstat (limited to 'rtl/src/verilog')
| -rw-r--r-- | rtl/src/verilog/core_selector.v | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 7f92e43..092b8ca 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -48,12 +48,15 @@ module core_selector input wire [31 : 0] write_data ); + parameter SHA256_BASE = 6'h14; + wire is_sha256 = ~(sys_eim_addr[13:8] ^ SHA256_BASE); + wire sha256_cs = (is_sha256 & sys_eim_rd) | (is_sha256 & sys_eim_wr); sha256 sha256_inst( .clk(sys_clk), .reset_n(~sys_rst), - .cs(sys_eim_rd | sys_eim_wr), + .cs(sha256_cs), .we(sys_eim_wr), .address(sys_eim_addr[7 : 0]), |