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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-03-13 13:36:15 +0100
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-03-13 13:36:15 +0100
commit0bdca3b2132d1ebbf90277a6613daefbeb397548 (patch)
tree5b92dbfe61d4dbb927a1be3fd9227ef6dfc23d2b /rtl/src/verilog/eim_memory.v
parent97f033586d90b3b6002c54f2cbd5854707fb0d5f (diff)
Fixed names for core selector to follow the form of the selectors for rng and ciphers. Fixed copy crimes. Disabled hash cores for the time being since we want to debug the rng.trng
Diffstat (limited to 'rtl/src/verilog/eim_memory.v')
-rw-r--r--rtl/src/verilog/eim_memory.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/rtl/src/verilog/eim_memory.v b/rtl/src/verilog/eim_memory.v
index 953cff3..60ca57f 100644
--- a/rtl/src/verilog/eim_memory.v
+++ b/rtl/src/verilog/eim_memory.v
@@ -109,7 +109,7 @@ module eim_memory
// EIM address space and select which core to send EIM read and
// write operations to.
//----------------------------------------------------------------
- core_selector segment_cores
+ hash_selector segment_hashes
(
.sys_clk(sys_clk),
.sys_rst(sys_rst),