diff options
| author | Joachim StroĢmbergson <joachim@secworks.se> | 2015-01-31 09:03:06 +0100 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2015-01-31 09:03:06 +0100 |
| commit | a68ffdd6c327bcc5d0c0524c4dacd6ceeaf839d7 (patch) | |
| tree | 2fc4876ab32718ce45943e960fbd1f8be16eb1d5 /rtl/src/verilog/eim_indicator.v | |
| parent | 785767f35cdee9aca04969b97734e05351bb084d (diff) | |
Adding all main hw source files and constraints.
Diffstat (limited to 'rtl/src/verilog/eim_indicator.v')
| -rw-r--r-- | rtl/src/verilog/eim_indicator.v | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/rtl/src/verilog/eim_indicator.v b/rtl/src/verilog/eim_indicator.v new file mode 100644 index 0000000..1324afb --- /dev/null +++ b/rtl/src/verilog/eim_indicator.v @@ -0,0 +1,36 @@ +`timescale 1ns / 1ps
+
+module eim_indicator
+ (
+ sys_clk, sys_rst,
+ eim_active,
+ led_out
+ );
+
+ //
+ // Ports
+ //
+ input wire sys_clk;
+ input wire sys_rst;
+ input wire eim_active;
+ output wire led_out;
+
+ //
+ // Parameters
+ //
+ localparam CNT_BITS = 24; // led will be dim for 2**(24-1) = 8388608 ticks, which is ~100 ms @ 80 MHz.
+
+ //
+ // Counter
+ //
+ reg [CNT_BITS-1:0] cnt;
+
+ always @(posedge sys_clk)
+ //
+ if (sys_rst) cnt <= {CNT_BITS{1'b0}};
+ else if (cnt > {CNT_BITS{1'b0}}) cnt <= cnt - 1'b1;
+ else if (eim_active) cnt <= {CNT_BITS{1'b1}};
+
+ assign led_out = ~cnt[CNT_BITS-1];
+
+endmodule
|