Updates from Pavel with new mux.

1. EIM arbiter was updated to take advantage of 3 additional address
lines, that bunnie routed from the CPU to the FPGA. Now we have 19 address
lines instead of 16, that means 19-2=17 effective bits when using 32-bit
access.

2. In the doc directory there's a draft version of current EIM memory map.

3. I've figured out why you guys could not use read and write signals from
the arbiter the way they were supposed to be used. I was wrong when I
expected Joachim's cores to have registered outputs. They have a
combinatorial output in fact. EIM arbiter's minimum latency is 1 cycle, so
we have to register data coming out of cores. I've added these three lines
to every core wrapper (sha1.v, sha256.v and sha512.v):
  reg [31 : 0]   tmp_read_data_reg;
  always @(posedge clk) tmp_read_data_reg <= tmp_read_data;
  assign read_data = tmp_read_data_reg;

4. Joachim told me, that we are going to have different types of cores
(HASH, RNG, CIPHER and so on), so I redesigned EIM multiplexor to have
separate modules for every core type. RNG and CIPHER selectors right now
are just templates with some dummy registers. Here is what was modified in
the HASH multiplexor:

4a. Core number 0 was added. It is not an actual HASH core, but a set of
global (board-level) registers. I've added three registers so far: board
type, bitstream version and one writeable dummy general-purpose register.

4b. Core instantiation was made conditional to allow selecting of what
cores to actually implement. We can have a project that offers a large
number of cores, so people can disable unnecessary cores to speed up
compile time and to save some slices for something else.

4c. I have disconnected .error() output from cores. As far as I understand
it gets asserted when some non-existent register is being addressed. In
most projects that I've seen writes to empty regions of memory are
discarded and reads return zeroes. If you really need this kind of error
checking, please re-connect this output as needed.

4d. core_selector.v has an instruction on how to add new HASH cores to our
design.

5. TC11() was added to hash_tester.c to check that we can read global
board-level registers and that we have access to segments other than
HASH. The last check reads dummy registers from RNG and CIPHER segments
(which are just templates now), this effectively tests the 3 new added
address bits.

1 files changed, 14 insertions, 14 deletions

diff --git a/rtl/src/verilog/eim_arbiter_cdc.v b/rtl/src/verilog/eim_arbiter_cdc.v
index c9df62e..a0412fe 100644
--- a/rtl/src/verilog/eim_arbiter_cdc.v
+++ b/rtl/src/verilog/eim_arbiter_cdc.v
@@ -49,11 +49,11 @@ module eim_arbiter_cdc
 	input		wire				eim_clk;			// eim clock
 	input		wire				eim_req;			// eim transaction request
 	output	wire				eim_ack;			// eim transaction acknowledge
-	input		wire	[47: 0]	eim_din;			// data from cpu to fpga (write access)
+	input		wire	[50: 0]	eim_din;			// data from cpu to fpga (write access)
 	output	wire	[31: 0]	eim_dout;		// data from fpga to cpu (read access)
 
 	input		wire				sys_clk;			// user internal clock
-	output	wire	[13: 0]	sys_addr;		// user access address
+	output	wire	[16: 0]	sys_addr;		// user access address
 	output	wire				sys_wren;		// user write flag
 	output	wire	[31: 0]	sys_data_out;	// user write data
 	output	wire				sys_rden;		// user read flag
@@ -64,11 +64,11 @@ module eim_arbiter_cdc
 		// EIM_CLK -> SYS_CLK Request
 		//
 	wire				sys_req;		// request pulse in sys_clk clock domain
-	wire	[47: 0]	sys_dout;	// transaction data in sys_clk clock domain
+	wire	[50: 0]	sys_dout;	// transaction data in sys_clk clock domain
 
 	cdc_bus_pulse #
 	(
-		.DATA_WIDTH		(48)	// {write, read, addr, data}
+		.DATA_WIDTH		(51)	// {write, read, msb addr, lsb addr, data}
 	)
 	cdc_eim_sys
 	(
@@ -85,16 +85,16 @@ module eim_arbiter_cdc
 		//
 		// Output Registers
 		//
-	reg	[13: 0]	sys_addr_reg		= {14{1'bX}};	//
-	reg				sys_wren_reg		= 1'b0;			//
+	reg				sys_wren_reg		= 1'b0;			//

+	reg				sys_rden_reg		= 1'b0;			//

+	reg	[16: 0]	sys_addr_reg		= {17{1'bX}};	//
 	reg	[31: 0]	sys_data_out_reg	= {32{1'bX}};	//
-	reg				sys_rden_reg		= 1'b0;			//
-
+	

+	assign sys_wren		= sys_wren_reg;

+	assign sys_rden		= sys_rden_reg;
 	assign sys_addr		= sys_addr_reg;
-	assign sys_wren		= sys_wren_reg;
 	assign sys_data_out	= sys_data_out_reg;
-	assign sys_rden		= sys_rden_reg;
-
+	
 
 		//
 		// System (User) Clock Access Handler
@@ -102,10 +102,10 @@ module eim_arbiter_cdc
 	always @(posedge sys_clk)
 		//
 		if (sys_req) begin									// request detected?
-			sys_wren_reg		<= sys_dout[47];				// set write flag if needed
-			sys_addr_reg		<= sys_dout[45:32];			// set operation address
+			sys_wren_reg		<= sys_dout[50];				// set write flag if needed

+			sys_rden_reg		<= sys_dout[49];				// set read flag if needed
+			sys_addr_reg		<= sys_dout[48:32];			// set operation address
 			sys_data_out_reg	<= sys_dout[31: 0];			// set data to write
-			sys_rden_reg		<= sys_dout[46];				// set read flag if needed
 		end else begin											// no request active
 			sys_wren_reg		<=  1'b0;						// clear write flag
 			sys_rden_reg		<=  1'b0;						// clear read flag