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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-02-02 15:30:01 +0100
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-02-02 15:30:01 +0100
commitbe2f38da52b2b4d0c0ce282ea15f1100d11a81ec (patch)
treeba809e9558459839d9606ac196f984f5a8315079 /rtl/src/testbench
parent7e6657d37db9742d3e6e943b3f01d781a7aa3538 (diff)
Changing to Verilog 2001 style interface. Changed port names to not have inports called ootput etc. Read and write is better.
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