Merge branch 'coretest_hashes' of git.cryptech.is:test/novena_base into master

1 files changed, 17 insertions, 5 deletions

diff --git a/rtl/src/testbench/tb_demo_adder.v b/rtl/src/testbench/tb_demo_adder.v
index 5abbf06..76771a5 100644
--- a/rtl/src/testbench/tb_demo_adder.v
+++ b/rtl/src/testbench/tb_demo_adder.v
@@ -24,6 +24,7 @@ module tb_demo_adder;
 	wire	[15: 0]	eim_da;

 	reg	[15: 0]	eim_da_out;

 	reg				eim_da_drive;

+	reg	[18:16]	eim_a;

 	reg				eim_oe_n;

 	reg				eim_wr_n;

 	wire				eim_wait_n;

@@ -41,6 +42,7 @@ module tb_demo_adder;
 		.eim_bclk			(eim_bclk),

 		.eim_cs0_n			(eim_cs_n),

 		.eim_da				(eim_da),

+		.eim_a				(eim_a),

 		.eim_lba_n			(eim_lba_n),

 		.eim_wr_n			(eim_wr_n),

 		.eim_oe_n			(eim_oe_n),

@@ -66,6 +68,7 @@ module tb_demo_adder;
 		eim_lba_n		= 1'b1;

 		eim_da_out		= {16{1'bX}};

 		eim_da_drive	= 1'b1;

+		eim_a				= 3'bXXX;

 		eim_oe_n			= 1'b1;

 		eim_wr_n			= 1'b1;

 	end

@@ -81,6 +84,11 @@ module tb_demo_adder;
 		//

 		#2000;

 		//

+		eim_read(19'h10000, eim_rd);				// read Z				<-- should be 0xBB77B7B7

+		//

+		#10000;

+		//

+		/*

 		eim_write({12'h321, 2'd0, 2'b00}, 32'hAA_55_A5_A5);	// write X

 		#100;

 		eim_write({12'h321, 2'd1, 2'b00}, 32'h11_22_12_12);	// write Y

@@ -93,6 +101,7 @@ module tb_demo_adder;
 		eim_read( {12'h321, 2'd3, 2'b00}, eim_rd);				// read {STS, CTL}	<-- should be 0x0001_0001

 		#100;

 		eim_read( {12'h321, 2'd2, 2'b00}, eim_rd);				// read Z				<-- should be 0xBB77B7B7

+		*/

 	end	

 		

 		//

@@ -100,17 +109,19 @@ module tb_demo_adder;
 		//

 	integer wr;

 	task eim_write;

-		input [15: 0] addr;

+		input [18: 0] addr;

 		input [31: 0] data;

 		begin

 			#15	eim_cs_n		= 1'b0;

 					eim_lba_n	= 1'b0;

-					eim_da_out	= addr;

+					eim_da_out	= addr[15: 0];

+					eim_a			= addr[18:16];

 					eim_wr_n		= 1'b0;

 			#15	eim_bclk		= 1'b1;

 			#15	eim_bclk		= 1'b0;

 					eim_lba_n	= 1'b1;

 					eim_da_out	= data[15:0];

+					eim_a			= 3'bXXX;

 			#15	eim_bclk		= 1'b1;

 			#15	eim_bclk		= 1'b0;

 					eim_da_out	= data[31:16];

@@ -132,19 +143,20 @@ module tb_demo_adder;
 		// Read Access

 		//

 	task eim_read;

-		input  [15: 0] addr;

+		input  [18: 0] addr;

 		output [31: 0] data;

 		begin

 			#15	eim_cs_n			= 1'b0;

 					eim_lba_n		= 1'b0;

-					eim_da_out		= addr;

-					

+					eim_da_out		= addr[15: 0];

+					eim_a				= addr[18:16];

 			#15	eim_bclk			= 1'b1;

 			

 			#15	eim_bclk			= 1'b0;

 					eim_lba_n		= 1'b1;

 					eim_oe_n			= 1'b0;

 					eim_da_drive	= 1'b0;

+					eim_a				= 3'bXXX;

 			#15;

 			while (eim_wait_n == 1'b0) begin

 					eim_bclk		= 1'b1;