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authorPaul Selkirk <paul@psgd.org>2015-02-02 17:42:17 -0500
committerPaul Selkirk <paul@psgd.org>2015-02-02 17:42:17 -0500
commit82d5359aa8547b25e2b84dfc92481e4976d1954b (patch)
tree1a51e4783fed2bc460dbfdbcb08fd07f928e3aec /rtl/src/ipcore/_xmsgs
parentbe2f38da52b2b4d0c0ce282ea15f1100d11a81ec (diff)
update project file paths to .v and .ucf files
Diffstat (limited to 'rtl/src/ipcore/_xmsgs')
-rw-r--r--rtl/src/ipcore/_xmsgs/pn_parser.xmsgs15
1 files changed, 0 insertions, 15 deletions
diff --git a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
deleted file mode 100644
index 8fe7625..0000000
--- a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
+++ /dev/null
@@ -1,15 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- IMPORTANT: This is an internal file that has been generated -->
-<!-- by the Xilinx ISE software. Any direct editing or -->
-<!-- changes made to this file may result in unpredictable -->
-<!-- behavior or data corruption. It is strongly advised that -->
-<!-- users do not edit the contents of this file. -->
-<!-- -->
-<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
-
-<messages>
-<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;Z:/Sandbox/external/cryptech/test/novena_base/rtl/src/ipcore/tmp/_cg/clkmgr_dcm.v&quot; into library work</arg>
-</msg>
-
-</messages>
-