add all SHA cores (hello coretest_hashes)

1 files changed, 32 insertions, 0 deletions

diff --git a/rtl/build/Makefile b/rtl/build/Makefile
new file mode 100644
index 0000000..ec03197
--- /dev/null
+++ b/rtl/build/Makefile
@@ -0,0 +1,32 @@
+project = novena_baseline_top
+vendor = xilinx
+family = spartan6
+part = xc6slx45csg324-3
+top_module = novena_baseline_top
+isedir = /opt/Xilinx/14.7/ISE_DS
+xil_env = . $(isedir)/settings64.sh
+
+vfiles = \
+	../src/verilog/novena_baseline_top.v \
+	../src/verilog/novena_clkmgr.v \
+	../src/verilog/cdc_bus_pulse.v \
+	../src/verilog/eim_arbiter.v \
+	../src/verilog/eim_da_phy.v \
+	../src/verilog/eim_arbiter_cdc.v \
+	../src/verilog/core_selector.v \
+	../src/verilog/eim_indicator.v \
+	../src/ipcore/clkmgr_dcm.v \
+	../../../../core/sha256/src/rtl/sha256_core.v \
+	../../../../core/sha256/src/rtl/sha256_k_constants.v \
+	../../../../core/sha256/src/rtl/sha256.v \
+	../../../../core/sha256/src/rtl/sha256_w_mem.v \
+	../../../../core/sha1/src/rtl/sha1_core.v \
+	../../../../core/sha1/src/rtl/sha1.v \
+	../../../../core/sha1/src/rtl/sha1_w_mem.v \
+	../../../../core/sha512/src/rtl/sha512_core.v \
+	../../../../core/sha512/src/rtl/sha512_h_constants.v \
+	../../../../core/sha512/src/rtl/sha512_k_constants.v \
+	../../../../core/sha512/src/rtl/sha512.v \
+	../../../../core/sha512/src/rtl/sha512_w_mem.v
+
+include xilinx.mk