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authorPaul Selkirk <paul@psgd.org>2015-02-10 15:06:55 -0500
committerPaul Selkirk <paul@psgd.org>2015-02-10 15:06:55 -0500
commit5f769e9b78a61d6b69355a6aae8572128a8f54a3 (patch)
tree580ade697710dfad19586319c2e2639170f212f9
parent0e4e0b5d71b15e1f4edf31295fc95d45d4ae3890 (diff)
Reformat verilog code for readability.
Diffstat
-rw-r--r--rtl/src/verilog/cdc_bus_pulse.v199
-rw-r--r--rtl/src/verilog/cipher_selector.v134
-rw-r--r--rtl/src/verilog/core_selector.v388
-rw-r--r--rtl/src/verilog/eim_arbiter.v505
-rw-r--r--rtl/src/verilog/eim_arbiter_cdc.v200
-rw-r--r--rtl/src/verilog/eim_da_phy.v74
-rw-r--r--rtl/src/verilog/eim_indicator.v49
-rw-r--r--rtl/src/verilog/eim_memory.v266
-rw-r--r--rtl/src/verilog/novena_baseline_top.v284
-rw-r--r--rtl/src/verilog/novena_clkmgr.v142
-rw-r--r--rtl/src/verilog/novena_regs.v198
-rw-r--r--rtl/src/verilog/rng_selector.v128
-rw-r--r--rtl/src/verilog/sha1.v98
-rw-r--r--rtl/src/verilog/sha256.v98
-rw-r--r--rtl/src/verilog/sha512.v116
15 files changed, 1467 insertions, 1412 deletions
diff --git a/rtl/src/verilog/cdc_bus_pulse.v b/rtl/src/verilog/cdc_bus_pulse.v
index 6f1fa34..cc2d8db 100644
--- a/rtl/src/verilog/cdc_bus_pulse.v
+++ b/rtl/src/verilog/cdc_bus_pulse.v
@@ -11,7 +11,7 @@
//
//
// Author: Pavel Shatov
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -42,109 +42,100 @@
//======================================================================
module cdc_bus_pulse
- (
- src_clk, src_din, src_req,
- dst_clk, dst_dout, dst_pulse
- );
-
- //
- // Parameters
- //
- parameter DATA_WIDTH = 32; // width of data bus
-
-
- //
- // Ports
- //
- input wire src_clk; // source domain clock
- input wire [DATA_WIDTH-1:0] src_din; // data from source clock domain
- input wire src_req; // start transfer pulse from source clock domain
-
- input wire dst_clk; // destination domain clock
- output wire [DATA_WIDTH-1:0] dst_dout; // data to destination clock domain
- output wire dst_pulse; // transfer done pulse to destination clock domain
-
-
- //
- // Source Side Registers
- //
- reg src_ff = 1'b0; // transfer request flag
- reg [DATA_WIDTH-1:0] src_latch = {DATA_WIDTH{1'bX}}; // source data buffer
-
-
- //
- // Source Request Handler
- //
- always @(posedge src_clk)
- //
- if (src_req) begin // transfer request pulse?
- src_ff <= ~src_ff; // toggle transfer request flag...
- src_latch <= src_din; // ... and capture data in source buffer
- end
-
-
- //
- // Source -> Destination Flag Sync Logic
- //
-
- /* ISE may decide to infer SRL here, so we explicitly instantiate slice registers. */
-
- wire flag_sync_first; // first FF output
- wire flag_sync_second; // second FF output
- wire flag_sync_third; // third FF output
- wire flag_sync_pulse; // flag toggle detector output
-
- FDCE ff_sync_first
- (
- .C (dst_clk),
- .D (src_ff), // capture flag from another clock domain
- .Q (flag_sync_first), // metastability can occur here
- .CLR (1'b0),
- .CE (1'b1)
- );
- FDCE ff_sync_second
- (
- .C (dst_clk),
- .D (flag_sync_first), // synchronize captured flag to remove metastability
- .Q (flag_sync_second), // and pass it to another flip-flop
- .CLR (1'b0),
- .CE (1'b1)
- );
- FDCE ff_sync_third
- (
- .C (dst_clk),
- .D (flag_sync_second), // delay synchronized flag in another flip-flip, because we need
- .Q (flag_sync_third), // two synchronized flag values (current and delayed) to detect its change
- .CLR (1'b0),
- .CE (1'b1)
- );
-
- // when delayed flag value differs from its current value, it was changed
- // by the source side, so there must have been a transfer request
- assign flag_sync_pulse = flag_sync_second ^ flag_sync_third;
-
-
- //
- // Destination Side Registers
- //
- reg dst_pulse_reg = 1'b0; // transfer done flag
- reg [DATA_WIDTH-1:0] dst_latch = {DATA_WIDTH{1'bX}}; // destination data buffer
-
- assign dst_pulse = dst_pulse_reg;
- assign dst_dout = dst_latch;
-
- //
- // Destination Request Handler
- //
- always @(posedge dst_clk) begin
- //
- dst_pulse_reg <= flag_sync_pulse; // generate pulse if flag change was detected
- //
- if (flag_sync_pulse) dst_latch <= src_latch; // by the time destination side receives synchronized
- // // flag value, data should be stable, we can safely
- // // capture and store it in the destination buffer
- //
- end
+ #(parameter DATA_WIDTH = 32) // width of data bus
+ (
+ input wire src_clk, // source domain clock
+ input wire [DATA_WIDTH-1:0] src_din, // data from source clock domain
+ input wire src_req, // start transfer pulse from source clock domain
+
+ input wire dst_clk, // destination domain clock
+ output wire [DATA_WIDTH-1:0] dst_dout, // data to destination clock domain
+ output wire dst_pulse // transfer done pulse to destination clock domain
+ );
+
+ //
+ // Source Side Registers
+ //
+ reg src_ff = 1'b0; // transfer request flag
+ reg [DATA_WIDTH-1:0] src_latch = {DATA_WIDTH{1'bX}}; // source data buffer
+
+
+ //
+ // Source Request Handler
+ //
+ always @(posedge src_clk)
+ //
+ if (src_req) begin // transfer request pulse?
+ src_ff <= ~src_ff; // toggle transfer request flag...
+ src_latch <= src_din; // ... and capture data in source buffer
+ end
+
+
+ //
+ // Source -> Destination Flag Sync Logic
+ //
+
+ /* ISE may decide to infer SRL here, so we explicitly instantiate slice registers. */
+
+ wire flag_sync_first; // first FF output
+ wire flag_sync_second; // second FF output
+ wire flag_sync_third; // third FF output
+ wire flag_sync_pulse; // flag toggle detector output
+
+ FDCE ff_sync_first
+ (
+ .C(dst_clk),
+ .D(src_ff), // capture flag from another clock domain
+ .Q(flag_sync_first), // metastability can occur here
+ .CLR(1'b0),
+ .CE(1'b1)
+ );
+ FDCE ff_sync_second
+ (
+ .C(dst_clk),
+ .D(flag_sync_first), // synchronize captured flag to remove metastability
+ .Q(flag_sync_second), // and pass it to another flip-flop
+ .CLR(1'b0),
+ .CE(1'b1)
+ );
+ FDCE ff_sync_third
+ (
+ .C(dst_clk),
+ .D(flag_sync_second), // delay synchronized flag in another flip-flip, because we need
+ .Q(flag_sync_third), // two synchronized flag values (current and delayed) to detect its change
+ .CLR(1'b0),
+ .CE(1'b1)
+ );
+
+ // when delayed flag value differs from its current value, it was changed
+ // by the source side, so there must have been a transfer request
+ assign flag_sync_pulse = flag_sync_second ^ flag_sync_third;
+
+
+ //
+ // Destination Side Registers
+ //
+ reg dst_pulse_reg = 1'b0; // transfer done flag
+ reg [DATA_WIDTH-1:0] dst_latch = {DATA_WIDTH{1'bX}}; // destination data buffer
+
+ assign dst_pulse = dst_pulse_reg;
+ assign dst_dout = dst_latch;
+
+ //
+ // Destination Request Handler
+ //
+ always @(posedge dst_clk) begin
+ //
+ dst_pulse_reg <= flag_sync_pulse; // generate pulse if flag change was detected
+ //
+ if (flag_sync_pulse)
+ dst_latch <= src_latch;
+ /* By the time destination side receives synchronized flag
+ * value, data should be stable, we can safely capture and store
+ * it in the destination buffer.
+ */
+
+ end
endmodule
diff --git a/rtl/src/verilog/cipher_selector.v b/rtl/src/verilog/cipher_selector.v
index 31dfe4b..ea18e14 100644
--- a/rtl/src/verilog/cipher_selector.v
+++ b/rtl/src/verilog/cipher_selector.v
@@ -40,73 +40,75 @@
//======================================================================
module cipher_selector
- (
- input wire sys_clk,
- input wire sys_rst,
- input wire sys_ena,
+ (
+ input wire sys_clk,
+ input wire sys_rst,
+ input wire sys_ena,
- input wire [13: 0] sys_eim_addr,
- input wire sys_eim_wr,
- input wire sys_eim_rd,
- output wire [31 : 0] sys_read_data,
- input wire [31 : 0] sys_write_data
- );
-
-
- //
- // Output Register
- //
- reg [31: 0] tmp_read_data;
- assign sys_read_data = tmp_read_data;
-
-
- /* So far we have no CIPHER cores, let's make some dummy 32-bit registers here
- * to prevent ISE from complaining that we don't use input ports.
- */
-
- reg [31: 0] reg_dummy_first;
- reg [31: 0] reg_dummy_second;
- reg [31: 0] reg_dummy_third;
-
- always @(posedge sys_clk)
- //
- if (sys_rst) begin
- reg_dummy_first <= {8{4'hD}};
- reg_dummy_second <= {8{4'hE}};
- reg_dummy_third <= {8{4'hF}};
- end else if (sys_ena) begin
- //
- if (sys_eim_wr) begin
- //
- // WRITE handler
- //
- case (sys_eim_addr)
- 14'd0: reg_dummy_first <= sys_write_data;
- 14'd1: reg_dummy_second <= sys_write_data;
- 14'd2: reg_dummy_third <= sys_write_data;
- endcase
- //
- end
- //
- if (sys_eim_rd) begin
- //
- // READ handler
- //
- case (sys_eim_addr)
- 14'd0: tmp_read_data <= reg_dummy_first;
- 14'd1: tmp_read_data <= reg_dummy_second;
- 14'd2: tmp_read_data <= reg_dummy_third;
- //
- default: tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
- /*
- default: tmp_read_data <= {32{1'bX}}; // don't care what to read from non-existent locations
- */
- endcase
- //
- end
- //
- end
-
+ input wire [13: 0] sys_eim_addr,
+ input wire sys_eim_wr,
+ input wire sys_eim_rd,
+ output wire [31 : 0] sys_read_data,
+ input wire [31 : 0] sys_write_data
+ );
+
+
+ //
+ // Output Register
+ //
+ reg [31: 0] tmp_read_data;
+ assign sys_read_data = tmp_read_data;
+
+
+ /* So far we have no CIPHER cores, let's make some dummy 32-bit registers here
+ * to prevent ISE from complaining that we don't use input ports.
+ */
+
+ reg [31: 0] reg_dummy_first;
+ reg [31: 0] reg_dummy_second;
+ reg [31: 0] reg_dummy_third;
+
+ always @(posedge sys_clk)
+ //
+ if (sys_rst)
+ begin
+ reg_dummy_first <= {8{4'hD}};
+ reg_dummy_second <= {8{4'hE}};
+ reg_dummy_third <= {8{4'hF}};
+ end
+ else if (sys_ena)
+ begin
+ //
+ if (sys_eim_wr)
+ begin
+ //
+ // WRITE handler
+ //
+ case (sys_eim_addr)
+ 14'd0: reg_dummy_first <= sys_write_data;
+ 14'd1: reg_dummy_second <= sys_write_data;
+ 14'd2: reg_dummy_third <= sys_write_data;
+ endcase
+ //
+ end
+ //
+ if (sys_eim_rd)
+ begin
+ //
+ // READ handler
+ //
+ case (sys_eim_addr)
+ 14'd0: tmp_read_data <= reg_dummy_first;
+ 14'd1: tmp_read_data <= reg_dummy_second;
+ 14'd2: tmp_read_data <= reg_dummy_third;
+ //
+ default: tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
+ endcase
+ //
+ end
+ //
+ end
+
endmodule
diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v
index 8ac8909..eef0a75 100644
--- a/rtl/src/verilog/core_selector.v
+++ b/rtl/src/verilog/core_selector.v
@@ -40,202 +40,220 @@
//======================================================================
module core_selector
- (
- input wire sys_clk,
- input wire sys_rst,
- input wire sys_ena,
-
- input wire [13: 0] sys_eim_addr,
- input wire sys_eim_wr,
- input wire sys_eim_rd,
- output wire [31 : 0] sys_read_data,
- input wire [31 : 0] sys_write_data
- );
-
-
- /* In this memory segment (HASHES) we have 14 address bits. Every core has 8-bit internal address space,
- * so we can have up to 2^(14-8) = 64 cores here.
- *
- * Core #0 is not an actual HASH core, but a set of board-level (global) registers, that can be used to
- * get information about hardware (board type, bitstream version and so on).
- *
- * So far we have three cores: SHA-1, SHA-256 and SHA-512.
- */
-
- /*********************************************************
- * To add new HASH core named XXX follow the steps below *
- *********************************************************
- *
- * 1. Add corresponding `define under "List of Available Cores", this will allow users to exclude your
- * core from implementation to save some slices in case they don't need it.
- *
- * `define USE_CORE_XXX
- *
- *
- * 2. Choose address of your new core and add corresponding line under "Core Address Table". Core addresses
- * can be in the range from 1 to 63 inclusively. Core address 0 is reserved for a page of global registers
- * and must not be used.
- *
- * localparam CORE_ADDR_XXX = 6'dN;
- *
- *
- * 3. Add instantiation of your new core after all existing cores surrounded by conditional synthesis directives.
- * You also need a 32-bit output (read data) bus for your core and an enable flag. Note that sys_rst in
- * an active-high sync reset signal.
- *
- * `ifdef USE_CORE_XXX
- * wire [31: 0] read_data_xxx;
- * wire enable_xxx = sys_ena && (addr_core_num == CORE_ADDR_XXX);
- * xxx xxx_inst
- * (
- * .clk(sys_clk),
- * .reset_n(~sys_rst),
- * .cs(enable_xxx & (sys_eim_rd | sys_eim_wr)),
- * .we(sys_eim_wr),
- * .address(addr_core_reg),
- * .write_data(sys_write_data),
- * .read_data(read_data_xxx),
- * .error()
- * );
- * `endif
- *
- *
- * 4. Add previously created data bus to "Output (Read Data) Multiplexor" in the end of this file.
- *
- * `ifdef USE_CORE_XXX CORE_ADDR_XXX: sys_read_data_mux = read_data_xxx; `endif
- *
- */
-
-
- //----------------------------------------------------------------
- // Address Decoder
- //----------------------------------------------------------------
- wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; // upper 6 bits specify core being addressed
- wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; // lower 8 bits specify register offset in core
-
-
- /* We can comment following lines to exclude cores from implementation
- * in case we run out of slices.
- */
-
- //----------------------------------------------------------------
- // List of Available Cores
- //----------------------------------------------------------------
- `define USE_CORE_SHA1
- `define USE_CORE_SHA256
- `define USE_CORE_SHA512
-
-
- //----------------------------------------------------------------
- // Core Address Table
- //----------------------------------------------------------------
- localparam CORE_ADDR_GLOBAL_REGS = 6'd0;
- localparam CORE_ADDR_SHA1 = 6'd1;
- localparam CORE_ADDR_SHA256 = 6'd2;
- localparam CORE_ADDR_SHA512 = 6'd3;
-
-
- //----------------------------------------------------------------
- // Global Registers
- //----------------------------------------------------------------
- wire [31: 0] read_data_global;
- wire enable_global = sys_ena && (addr_core_num == CORE_ADDR_GLOBAL_REGS);
- novena_regs novena_regs_inst
- (
- .clk(sys_clk),
- .rst(sys_rst),
-
- .cs(enable_global & (sys_eim_rd | sys_eim_wr)),
+ (
+ input wire sys_clk,
+ input wire sys_rst,
+ input wire sys_ena,
+
+ input wire [13 : 0] sys_eim_addr,
+ input wire sys_eim_wr,
+ input wire sys_eim_rd,
+ output wire [31 : 0] sys_read_data,
+ input wire [31 : 0] sys_write_data
+ );
+
+
+ /* In this memory segment (HASHES) we have 14 address bits. Every core has
+ * 8-bit internal address space, so we can have up to 2^(14-8) = 64 cores here.
+ *
+ * Core #0 is not an actual HASH core, but a set of board-level (global)
+ * registers, that can be used to get information about hardware (board
+ * type, bitstream version and so on).
+ *
+ * So far we have three cores: SHA-1, SHA-256 and SHA-512.
+ */
+
+ /*********************************************************
+ * To add new HASH core named XXX follow the steps below *
+ *********************************************************
+ *
+ * 1. Add corresponding `define under "List of Available Cores", this will
+ * allow users to exclude your core from implementation to save some
+ * slices in case they don't need it.
+ *
+ * `define USE_CORE_XXX
+ *
+ *
+ * 2. Choose address of your new core and add corresponding line under
+ * "Core Address Table". Core addresses can be in the range from 1 to 63
+ * inclusively. Core address 0 is reserved for a page of global
+ * registers and must not be used.
+ *
+ * localparam CORE_ADDR_XXX = 6'dN;
+ *
+ *
+ * 3. Add instantiation of your new core after all existing cores
+ * surrounded by conditional synthesis directives.
+ * You also need a 32-bit output (read data) bus for your core and an
+ * enable flag. Note that sys_rst in an active-high sync reset signal.
+ *
+ * `ifdef USE_CORE_XXX
+ * wire [31: 0] read_data_xxx;
+ * wire enable_xxx = sys_ena && (addr_core_num == CORE_ADDR_XXX);
+ * xxx xxx_inst
+ * (
+ * .clk(sys_clk),
+ * .reset_n(~sys_rst),
+ * .cs(enable_xxx & (sys_eim_rd | sys_eim_wr)),
+ * .we(sys_eim_wr),
+ * .address(addr_core_reg),
+ * .write_data(sys_write_data),
+ * .read_data(read_data_xxx),
+ * .error()
+ * );
+ * `endif
+ *
+ *
+ * 4. Add previously created data bus to "Output (Read Data) Multiplexor"
+ * in the end of this file.
+ *
+ * `ifdef USE_CORE_XXX
+ * CORE_ADDR_XXX:
+ * sys_read_data_mux = read_data_xxx;
+ * `endif
+ *
+ */
+
+
+ //----------------------------------------------------------------
+ // Address Decoder
+ //----------------------------------------------------------------
+ wire [ 5: 0] addr_core_num = sys_eim_addr[13: 8]; // upper 6 bits specify core being addressed
+ wire [ 7: 0] addr_core_reg = sys_eim_addr[ 7: 0]; // lower 8 bits specify register offset in core
+
+
+ /* We can comment following lines to exclude cores from implementation
+ * in case we run out of slices.
+ */
+
+ //----------------------------------------------------------------
+ // List of Available Cores
+ //----------------------------------------------------------------
+ `define USE_CORE_SHA1
+ `define USE_CORE_SHA256
+ `define USE_CORE_SHA512
+
+
+ //----------------------------------------------------------------
+ // Core Address Table
+ //----------------------------------------------------------------
+ localparam CORE_ADDR_GLOBAL_REGS = 6'd0;
+ localparam CORE_ADDR_SHA1 = 6'd1;
+ localparam CORE_ADDR_SHA256 = 6'd2;
+ localparam CORE_ADDR_SHA512 = 6'd3;
+
+
+ //----------------------------------------------------------------
+ // Global Registers
+ //----------------------------------------------------------------
+ wire [31: 0] read_data_global;
+ wire enable_global = sys_ena && (addr_core_num == CORE_ADDR_GLOBAL_REGS);
+ novena_regs novena_regs_inst
+ (
+ .clk(sys_clk),
+ .rst(sys_rst),
+
+ .cs(enable_global & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
- .address(addr_core_reg),
- .write_data(sys_write_data),
- .read_data(read_data_global)
- );
-
-
- //----------------------------------------------------------------
- // SHA-1
- //----------------------------------------------------------------
- `ifdef USE_CORE_SHA1
- wire [31: 0] read_data_sha1;
- wire enable_sha1 = sys_ena && (addr_core_num == CORE_ADDR_SHA1);
- sha1 sha1_inst
- (
- .clk(sys_clk),
- .reset_n(~sys_rst),
-
- .cs(enable_sha1 & (sys_eim_rd | sys_eim_wr)),
+ .address(addr_core_reg),
+ .write_data(sys_write_data),
+ .read_data(read_data_global)
+ );
+
+
+ //----------------------------------------------------------------
+ // SHA-1
+ //----------------------------------------------------------------
+ `ifdef USE_CORE_SHA1
+ wire [31: 0] read_data_sha1;
+ wire enable_sha1 = sys_ena && (addr_core_num == CORE_ADDR_SHA1);
+ sha1 sha1_inst
+ (
+ .clk(sys_clk),
+ .reset_n(~sys_rst),
+
+ .cs(enable_sha1 & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
- .address(addr_core_reg),
- .write_data(sys_write_data),
+ .address(addr_core_reg),
+ .write_data(sys_write_data),
.read_data(read_data_sha1)
- );
- `endif
-
-
- //----------------------------------------------------------------
- // SHA-256
- //----------------------------------------------------------------
- `ifdef USE_CORE_SHA256
- wire [31: 0] read_data_sha256;
- wire enable_sha256 = sys_ena && (addr_core_num == CORE_ADDR_SHA256);
- sha256 sha256_inst
- (
- .clk(sys_clk),
- .reset_n(~sys_rst),
-
- .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)),
+ );
+ `endif
+
+
+ //----------------------------------------------------------------
+ // SHA-256
+ //----------------------------------------------------------------
+ `ifdef USE_CORE_SHA256
+ wire [31: 0] read_data_sha256;
+ wire enable_sha256 = sys_ena && (addr_core_num == CORE_ADDR_SHA256);
+ sha256 sha256_inst
+ (
+ .clk(sys_clk),
+ .reset_n(~sys_rst),
+
+ .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
- .address(addr_core_reg),
- .write_data(sys_write_data),
+ .address(addr_core_reg),
+ .write_data(sys_write_data),
.read_data(read_data_sha256)
- );
- `endif
-
-
- //----------------------------------------------------------------
- // SHA-512
- //----------------------------------------------------------------
- `ifdef USE_CORE_SHA512
- wire [31: 0] read_data_sha512;
- wire enable_sha512 = sys_ena && (addr_core_num == CORE_ADDR_SHA512);
- sha512 sha512_inst
- (
- .clk(sys_clk),
- .reset_n(~sys_rst),
-
- .cs(enable_sha512 & (sys_eim_rd | sys_eim_wr)),
+ );
+ `endif
+
+
+ //----------------------------------------------------------------
+ // SHA-512
+ //----------------------------------------------------------------
+ `ifdef USE_CORE_SHA512
+ wire [31: 0] read_data_sha512;
+ wire enable_sha512 = sys_ena && (addr_core_num == CORE_ADDR_SHA512);
+ sha512 sha512_inst
+ (
+ .clk(sys_clk),
+ .reset_n(~sys_rst),
+
+ .cs(enable_sha512 & (sys_eim_rd | sys_eim_wr)),
.we(sys_eim_wr),
- .address(addr_core_reg),
- .write_data(sys_write_data),
+ .address(addr_core_reg),
+ .write_data(sys_write_data),
.read_data(read_data_sha512)
- );
- `endif
-
-
- //----------------------------------------------------------------
- // Output (Read Data) Multiplexor
- //----------------------------------------------------------------
- reg [31: 0] sys_read_data_mux;
- assign sys_read_data = sys_read_data_mux;
-
- always @*
- //
- case (addr_core_num)
- //
- CORE_ADDR_GLOBAL_REGS: sys_read_data_mux = read_data_global;
- `ifdef USE_CORE_SHA1 CORE_ADDR_SHA1: sys_read_data_mux = read_data_sha1; `endif
- `ifdef USE_CORE_SHA256 CORE_ADDR_SHA256: sys_read_data_mux = read_data_sha256; `endif
- `ifdef USE_CORE_SHA512 CORE_ADDR_SHA512: sys_read_data_mux = read_data_sha512; `endif
- //
- default: sys_read_data_mux = {32{1'b0}};
- //
- endcase
-
+ );
+ `endif
+
+
+ //----------------------------------------------------------------
+ // Output (Read Data) Multiplexor
+ //----------------------------------------------------------------
+ reg [31: 0] sys_read_data_mux;
+ assign sys_read_data = sys_read_data_mux;
+
+ always @*
+ //
+ case (addr_core_num)
+ //
+ CORE_ADDR_GLOBAL_REGS:
+ sys_read_data_mux = read_data_global;
+ `ifdef USE_CORE_SHA1
+ CORE_ADDR_SHA1:
+ sys_read_data_mux = read_data_sha1;
+ `endif
+ `ifdef USE_CORE_SHA256
+ CORE_ADDR_SHA256:
+ sys_read_data_mux = read_data_sha256;
+ `endif
+ `ifdef USE_CORE_SHA512
+ CORE_ADDR_SHA512:
+ sys_read_data_mux = read_data_sha512;
+ `endif
+ //
+ default:
+ sys_read_data_mux = {32{1'b0}};
+ //
+ endcase
endmodule
diff --git a/rtl/src/verilog/eim_arbiter.v b/rtl/src/verilog/eim_arbiter.v
index d21799f..e9b2c76 100644
--- a/rtl/src/verilog/eim_arbiter.v
+++ b/rtl/src/verilog/eim_arbiter.v
@@ -7,7 +7,7 @@
//
//
// Author: Pavel Shatov
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -38,249 +38,268 @@
//======================================================================
module eim_arbiter
- (
- eim_bclk, eim_cs0_n, eim_da, eim_a,
- eim_lba_n, eim_wr_n,
- eim_oe_n, eim_wait_n,
-
- sys_clk,
- sys_addr,
- sys_wren, sys_data_out,
- sys_rden, sys_data_in
- );
-
-
- //
- // Ports
- //
- input wire eim_bclk; // | eim bus
- input wire eim_cs0_n; // |
- inout wire [15: 0] eim_da; // |
- input wire [18:16] eim_a; // |
- input wire eim_lba_n; // |
- input wire eim_wr_n; // |
- input wire eim_oe_n; // |
- output wire eim_wait_n; // |
-
- input wire sys_clk; // system clock
-
- output wire [16: 0] sys_addr; // | user bus
- output wire sys_wren; // |
- output wire [31: 0] sys_data_out; // |
- output wire sys_rden; // |
- input wire [31: 0] sys_data_in; // |
-
-
- //
- // Data/Address PHY
- //
-
- /* PHY is needed to control bi-directional address/data bus. */
-
- wire [15: 0] da_ro; // value read from pins
- reg [15: 0] da_di; // value drives onto pins
-
- eim_da_phy da_phy
- (
- .buf_io (eim_da), // <-- connect directly top-level port
- .buf_di (da_di),
- .buf_ro (da_ro),
- .buf_t (eim_oe_n) // <-- driven by EIM directly
- );
-
-
- //
- // FSM
- //
- localparam EIM_FSM_STATE_INIT = 5'b0_0_000; // arbiter is idle
-
- localparam EIM_FSM_STATE_WRITE_START = 5'b1_1_000; // got address to write at
- localparam EIM_FSM_STATE_WRITE_LSB = 5'b1_1_001; // got lower 16 bits of data to write
- localparam EIM_FSM_STATE_WRITE_MSB = 5'b1_1_010; // got upper 16 bits of data to write
- localparam EIM_FSM_STATE_WRITE_WAIT = 5'b1_1_100; // request to user-side logic sent
- localparam EIM_FSM_STATE_WRITE_DONE = 5'b1_1_111; // user-side logic acknowledged transaction
-
- localparam EIM_FSM_STATE_READ_START = 5'b1_0_000; // got address to read from
- localparam EIM_FSM_STATE_READ_WAIT = 5'b1_0_100; // request to user-side logic sent
- localparam EIM_FSM_STATE_READ_READY = 5'b1_0_011; // got acknowledge from user logic
- localparam EIM_FSM_STATE_READ_LSB = 5'b1_0_001; // returned lower 16 bits to master
- localparam EIM_FSM_STATE_READ_MSB = 5'b1_0_010; // returned upper 16 bits to master
- localparam EIM_FSM_STATE_READ_DONE = 5'b1_0_111; // transaction complete
-
- reg [ 4: 0] eim_fsm_state = EIM_FSM_STATE_INIT; // fsm state
- reg [16: 0] eim_addr_latch = {17{1'bX}}; // transaction address
- reg [15: 0] eim_write_lsb_latch = {16{1'bX}}; // lower 16 bits of data to write
-
- /* These flags are used to wake up from INIT state. */
- wire eim_write_start_flag = (eim_lba_n == 1'b0) && (eim_wr_n == 1'b0) && (da_ro[1:0] == 2'b00);
- wire eim_read_start_flag = (eim_lba_n == 1'b0) && (eim_wr_n == 1'b1) && (da_ro[1:0] == 2'b00);
-
- /* These are transaction response flag and data from user-side logic. */
- wire eim_user_ack;
- wire [31: 0] eim_user_data;
-
- /* FSM is reset whenever Chip Select is de-asserted. */
-
- //
- // FSM Transition Logic
- //
- always @(posedge eim_bclk or posedge eim_cs0_n) begin
- //
- if (eim_cs0_n == 1'b1) eim_fsm_state <= EIM_FSM_STATE_INIT;
- //
- else begin
- //
- case (eim_fsm_state)
- //
- // INIT -> WRITE, INIT -> READ
- //
- EIM_FSM_STATE_INIT: begin
- if (eim_write_start_flag) eim_fsm_state <= EIM_FSM_STATE_WRITE_START;
- if (eim_read_start_flag) eim_fsm_state <= EIM_FSM_STATE_READ_START;
- end
- //
- // WRITE
- //
- EIM_FSM_STATE_WRITE_START: eim_fsm_state <= EIM_FSM_STATE_WRITE_LSB;
- //
- EIM_FSM_STATE_WRITE_LSB: eim_fsm_state <= EIM_FSM_STATE_WRITE_MSB;
- //
- EIM_FSM_STATE_WRITE_MSB: eim_fsm_state <= EIM_FSM_STATE_WRITE_WAIT;
- //
- EIM_FSM_STATE_WRITE_WAIT:
- if (eim_user_ack) eim_fsm_state <= EIM_FSM_STATE_WRITE_DONE;
- //
- EIM_FSM_STATE_WRITE_DONE: eim_fsm_state <= EIM_FSM_STATE_INIT;
- //
- // READ
- //
- EIM_FSM_STATE_READ_START: eim_fsm_state <= EIM_FSM_STATE_READ_WAIT;
- //
- EIM_FSM_STATE_READ_WAIT:
- if (eim_user_ack) eim_fsm_state <= EIM_FSM_STATE_READ_READY;
- //
- EIM_FSM_STATE_READ_READY: eim_fsm_state <= EIM_FSM_STATE_READ_LSB;
- //
- EIM_FSM_STATE_READ_LSB: eim_fsm_state <= EIM_FSM_STATE_READ_MSB;
- //
- EIM_FSM_STATE_READ_MSB: eim_fsm_state <= EIM_FSM_STATE_READ_DONE;
- //
- EIM_FSM_STATE_READ_DONE: eim_fsm_state <= EIM_FSM_STATE_INIT;
- //
- //
- //
- default: eim_fsm_state <= EIM_FSM_STATE_INIT;
- //
- endcase
- //
- end
- //
- end
-
-
- //
- // Address Latch
- //
- always @(posedge eim_bclk)
- //
- if ((eim_fsm_state == EIM_FSM_STATE_INIT) && (eim_write_start_flag || eim_read_start_flag))
- eim_addr_latch <= {eim_a[18:16], da_ro[15:2]};
-
-
- //
- // Additional Write Logic
- //
- always @(posedge eim_bclk)
- //
- if (eim_fsm_state == EIM_FSM_STATE_WRITE_START)
- eim_write_lsb_latch <= da_ro;
-
-
- //
- // Additional Read Logic
- //
-
- /* Note that this stuff operates on falling clock edge, because the cpu
+ (
+ // eim bus
+ input wire eim_bclk,
+ input wire eim_cs0_n,
+ inout wire [15: 0] eim_da,
+ input wire [18:16] eim_a,
+ input wire eim_lba_n,
+ input wire eim_wr_n,
+ input wire eim_oe_n,
+ output wire eim_wait_n,
+
+ // system clock
+ input wire sys_clk,
+
+ // user bus
+ output wire [16: 0] sys_addr,
+ output wire sys_wren,
+ output wire [31: 0] sys_data_out,
+ output wire sys_rden,
+ input wire [31: 0] sys_data_in
+ );
+
+
+ //
+ // Data/Address PHY
+ //
+
+ /* PHY is needed to control bi-directional address/data bus. */
+
+ wire [15: 0] da_ro; // value read from pins
+ reg [15: 0] da_di; // value drives onto pins
+
+ eim_da_phy da_phy
+ (
+ .buf_io(eim_da), // <-- connect directly top-level port
+ .buf_di(da_di),
+ .buf_ro(da_ro),
+ .buf_t(eim_oe_n) // <-- driven by EIM directly
+ );
+
+
+ //
+ // FSM
+ //
+ localparam EIM_FSM_STATE_INIT = 5'b0_0_000; // arbiter is idle
+
+ localparam EIM_FSM_STATE_WRITE_START = 5'b1_1_000; // got address to write at
+ localparam EIM_FSM_STATE_WRITE_LSB = 5'b1_1_001; // got lower 16 bits of data to write
+ localparam EIM_FSM_STATE_WRITE_MSB = 5'b1_1_010; // got upper 16 bits of data to write
+ localparam EIM_FSM_STATE_WRITE_WAIT = 5'b1_1_100; // request to user-side logic sent
+ localparam EIM_FSM_STATE_WRITE_DONE = 5'b1_1_111; // user-side logic acknowledged transaction
+
+ localparam EIM_FSM_STATE_READ_START = 5'b1_0_000; // got address to read from
+ localparam EIM_FSM_STATE_READ_WAIT = 5'b1_0_100; // request to user-side logic sent
+ localparam EIM_FSM_STATE_READ_READY = 5'b1_0_011; // got acknowledge from user logic
+ localparam EIM_FSM_STATE_READ_LSB = 5'b1_0_001; // returned lower 16 bits to master
+ localparam EIM_FSM_STATE_READ_MSB = 5'b1_0_010; // returned upper 16 bits to master
+ localparam EIM_FSM_STATE_READ_DONE = 5'b1_0_111; // transaction complete
+
+ reg [ 4: 0] eim_fsm_state = EIM_FSM_STATE_INIT; // fsm state
+ reg [16: 0] eim_addr_latch = {17{1'bX}}; // transaction address
+ reg [15: 0] eim_write_lsb_latch = {16{1'bX}}; // lower 16 bits of data to write
+
+ /* These flags are used to wake up from INIT state. */
+ wire eim_write_start_flag = (eim_lba_n == 1'b0) && (eim_wr_n == 1'b0) && (da_ro[1:0] == 2'b00);
+ wire eim_read_start_flag = (eim_lba_n == 1'b0) && (eim_wr_n == 1'b1) && (da_ro[1:0] == 2'b00);
+
+ /* These are transaction response flag and data from user-side logic. */
+ wire eim_user_ack;
+ wire [31: 0] eim_user_data;
+
+ /* FSM is reset whenever Chip Select is de-asserted. */
+
+ //
+ // FSM Transition Logic
+ //
+ always @(posedge eim_bclk or posedge eim_cs0_n)
+ begin
+ //
+ if (eim_cs0_n == 1'b1)
+ eim_fsm_state <= EIM_FSM_STATE_INIT;
+ //
+ else
+ begin
+ //
+ case (eim_fsm_state)
+ //
+ // INIT -> WRITE, INIT -> READ
+ //
+ EIM_FSM_STATE_INIT:
+ begin
+ if (eim_write_start_flag)
+ eim_fsm_state <= EIM_FSM_STATE_WRITE_START;
+ if (eim_read_start_flag)
+ eim_fsm_state <= EIM_FSM_STATE_READ_START;
+ end
+ //
+ // WRITE
+ //
+ EIM_FSM_STATE_WRITE_START:
+ eim_fsm_state <= EIM_FSM_STATE_WRITE_LSB;
+ //
+ EIM_FSM_STATE_WRITE_LSB:
+ eim_fsm_state <= EIM_FSM_STATE_WRITE_MSB;
+ //
+ EIM_FSM_STATE_WRITE_MSB:
+ eim_fsm_state <= EIM_FSM_STATE_WRITE_WAIT;
+ //
+ EIM_FSM_STATE_WRITE_WAIT:
+ if (eim_user_ack)
+ eim_fsm_state <= EIM_FSM_STATE_WRITE_DONE;
+ //
+ EIM_FSM_STATE_WRITE_DONE:
+ eim_fsm_state <= EIM_FSM_STATE_INIT;
+ //
+ // READ
+ //
+ EIM_FSM_STATE_READ_START:
+ eim_fsm_state <= EIM_FSM_STATE_READ_WAIT;
+ //
+ EIM_FSM_STATE_READ_WAIT:
+ if (eim_user_ack)
+ eim_fsm_state <= EIM_FSM_STATE_READ_READY;
+ //
+ EIM_FSM_STATE_READ_READY:
+ eim_fsm_state <= EIM_FSM_STATE_READ_LSB;
+ //
+ EIM_FSM_STATE_READ_LSB:
+ eim_fsm_state <= EIM_FSM_STATE_READ_MSB;
+ //
+ EIM_FSM_STATE_READ_MSB:
+ eim_fsm_state <= EIM_FSM_STATE_READ_DONE;
+ //
+ EIM_FSM_STATE_READ_DONE:
+ eim_fsm_state <= EIM_FSM_STATE_INIT;
+ //
+ //
+ //
+ default:
+ eim_fsm_state <= EIM_FSM_STATE_INIT;
+ //
+ endcase
+ //
+ end
+ //
+ end
+
+
+ //
+ // Address Latch
+ //
+ always @(posedge eim_bclk)
+ //
+ if ((eim_fsm_state == EIM_FSM_STATE_INIT) && (eim_write_start_flag || eim_read_start_flag))
+ eim_addr_latch <= {eim_a[18:16], da_ro[15:2]};
+
+
+ //
+ // Additional Write Logic
+ //
+ always @(posedge eim_bclk)
+ //
+ if (eim_fsm_state == EIM_FSM_STATE_WRITE_START)
+ eim_write_lsb_latch <= da_ro;
+
+
+ //
+ // Additional Read Logic
+ //
+
+ /* Note that this stuff operates on falling clock edge, because the cpu
* samples our bi-directional data bus on rising clock edge.
- */
-
- always @(negedge eim_bclk or posedge eim_cs0_n)
- //
- if (eim_cs0_n == 1'b1) da_di <= {16{1'bX}}; // don't care what to drive
- else begin
- //
- if (eim_fsm_state == EIM_FSM_STATE_READ_LSB) da_di <= eim_user_data[15: 0]; // drive lower 16 bits at first...
- if (eim_fsm_state == EIM_FSM_STATE_READ_MSB) da_di <= eim_user_data[31:16]; // ...then drive upper 16 bits
- //
- end
-
-
- //
- // Wait Logic
- //
-
- /* Note that this stuff operates on falling clock edge, because the cpu
- * samples our WAIT_N flag on rising clock edge.
- */
-
- reg eim_wait_reg = 1'b0;
-
- always @(negedge eim_bclk or posedge eim_cs0_n)
- //
- if (eim_cs0_n == 1'b1) eim_wait_reg <= 1'b0; // clear wait
- else begin
- //
- if (eim_fsm_state == EIM_FSM_STATE_WRITE_START) eim_wait_reg <= 1'b1; // start waiting for write to complete
- if (eim_fsm_state == EIM_FSM_STATE_READ_START) eim_wait_reg <= 1'b1; // start waiting for read to complete
- //
- if (eim_fsm_state == EIM_FSM_STATE_WRITE_DONE) eim_wait_reg <= 1'b0; // write transaction done
- if (eim_fsm_state == EIM_FSM_STATE_READ_READY) eim_wait_reg <= 1'b0; // read transaction done
- //
- if (eim_fsm_state == EIM_FSM_STATE_INIT) eim_wait_reg <= 1'b0; // fsm is idle, no need to wait any more
- //
- end
-
- assign eim_wait_n = ~eim_wait_reg;
-
-
- /* These flags are used to generate 1-cycle pulses to trigger CDC transaction.
- * Note that FSM goes from WRITE_LSB to WRITE_MSB and from READ_START to READ_WAIT
- * unconditionally, so these flags will always be active for 1 cycle only, which
- * is exactly what we need.
- */
-
- wire arbiter_write_req_pulse = (eim_fsm_state == EIM_FSM_STATE_WRITE_LSB) ? 1'b1 : 1'b0;
- wire arbiter_read_req_pulse = (eim_fsm_state == EIM_FSM_STATE_READ_START) ? 1'b1 : 1'b0;
-
- //
- // CDC Block
- //
-
- /* This block is used to transfer request data from BCLK clock domain to SYS_CLK clock domain and
- * then transfer acknowledge from SYS_CLK to BCLK clock domain in return. Af first 1+1+3+14+32 = 51 bits
- * are transfered, these are: write flag, read flag, msb part of address, lsb part of address, write data.
- * During read transaction some bogus write data is passed, which is not used later anyway. During read
- * requests 32 bits of data are returned, during write requests 32 bits of bogus data are returned,
- * that are never used later.
- */
-
- eim_arbiter_cdc eim_cdc
- (
- .eim_clk (eim_bclk),
-
- .eim_req (arbiter_write_req_pulse | arbiter_read_req_pulse),
- .eim_ack (eim_user_ack),
-
- .eim_din ({arbiter_write_req_pulse, arbiter_read_req_pulse, eim_addr_latch, da_ro, eim_write_lsb_latch}),
- .eim_dout (eim_user_data),
-
- .sys_clk (sys_clk),
- .sys_addr (sys_addr),
- .sys_wren (sys_wren),
- .sys_data_out (sys_data_out),
- .sys_rden (sys_rden),
- .sys_data_in (sys_data_in)
- );
+ */
+
+ always @(negedge eim_bclk or posedge eim_cs0_n)
+ //
+ if (eim_cs0_n == 1'b1) da_di <= {16{1'bX}}; // don't care what to drive
+ else begin
+ //
+ if (eim_fsm_state == EIM_FSM_STATE_READ_LSB)
+ da_di <= eim_user_data[15: 0]; // drive lower 16 bits at first...
+ if (eim_fsm_state == EIM_FSM_STATE_READ_MSB)
+ da_di <= eim_user_data[31:16]; // ...then drive upper 16 bits
+ //
+ end
+
+
+ //
+ // Wait Logic
+ //
+
+ /* Note that this stuff operates on falling clock edge, because the cpu
+ * samples our WAIT_N flag on rising clock edge.
+ */
+
+ reg eim_wait_reg = 1'b0;
+
+ always @(negedge eim_bclk or posedge eim_cs0_n)
+ //
+ if (eim_cs0_n == 1'b1)
+ eim_wait_reg <= 1'b0; // clear wait
+ else begin
+ //
+ if (eim_fsm_state == EIM_FSM_STATE_WRITE_START)
+ eim_wait_reg <= 1'b1; // start waiting for write to complete
+ if (eim_fsm_state == EIM_FSM_STATE_READ_START)
+ eim_wait_reg <= 1'b1; // start waiting for read to complete
+ //
+ if (eim_fsm_state == EIM_FSM_STATE_WRITE_DONE)
+ eim_wait_reg <= 1'b0; // write transaction done
+ if (eim_fsm_state == EIM_FSM_STATE_READ_READY)
+ eim_wait_reg <= 1'b0; // read transaction done
+ //
+ if (eim_fsm_state == EIM_FSM_STATE_INIT)
+ eim_wait_reg <= 1'b0; // fsm is idle, no need to wait any more
+ //
+ end
+
+ assign eim_wait_n = ~eim_wait_reg;
+
+
+ /* These flags are used to generate 1-cycle pulses to trigger CDC
+ * transaction. Note that FSM goes from WRITE_LSB to WRITE_MSB and from
+ * READ_START to READ_WAIT unconditionally, so these flags will always be
+ * active for 1 cycle only, which is exactly what we need.
+ */
+
+ wire arbiter_write_req_pulse = (eim_fsm_state == EIM_FSM_STATE_WRITE_LSB) ? 1'b1 : 1'b0;
+ wire arbiter_read_req_pulse = (eim_fsm_state == EIM_FSM_STATE_READ_START) ? 1'b1 : 1'b0;
+
+ //
+ // CDC Block
+ //
+
+ /* This block is used to transfer request data from BCLK clock domain to
+ * SYS_CLK clock domain and then transfer acknowledge from SYS_CLK to BCLK
+ * clock domain in return. Af first 1+1+3+14+32 = 51 bits are transfered,
+ * these are: write flag, read flag, msb part of address, lsb part of address,
+ * write data. During read transaction some bogus write data is passed,
+ * which is not used later anyway. During read requests 32 bits of data are
+ * returned, during write requests 32 bits of bogus data are returned, that
+ * are never used later.
+ */
+
+ eim_arbiter_cdc eim_cdc
+ (
+ .eim_clk(eim_bclk),
+
+ .eim_req(arbiter_write_req_pulse | arbiter_read_req_pulse),
+ .eim_ack(eim_user_ack),
+
+ .eim_din({arbiter_write_req_pulse, arbiter_read_req_pulse,
+ eim_addr_latch, da_ro, eim_write_lsb_latch}),
+ .eim_dout(eim_user_data),
+
+ .sys_clk(sys_clk),
+ .sys_addr(sys_addr),
+ .sys_wren(sys_wren),
+ .sys_data_out(sys_data_out),
+ .sys_rden(sys_rden),
+ .sys_data_in(sys_data_in)
+ );
endmodule
diff --git a/rtl/src/verilog/eim_arbiter_cdc.v b/rtl/src/verilog/eim_arbiter_cdc.v
index a0412fe..15dc433 100644
--- a/rtl/src/verilog/eim_arbiter_cdc.v
+++ b/rtl/src/verilog/eim_arbiter_cdc.v
@@ -7,7 +7,7 @@
//
//
// Author: Pavel Shatov
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -38,107 +38,103 @@
//======================================================================
module eim_arbiter_cdc
- (
- eim_clk, eim_req, eim_ack, eim_din, eim_dout,
- sys_clk, sys_addr,
- sys_wren, sys_data_out,
- sys_rden, sys_data_in
- );
-
-
- input wire eim_clk; // eim clock
- input wire eim_req; // eim transaction request
- output wire eim_ack; // eim transaction acknowledge
- input wire [50: 0] eim_din; // data from cpu to fpga (write access)
- output wire [31: 0] eim_dout; // data from fpga to cpu (read access)
-
- input wire sys_clk; // user internal clock
- output wire [16: 0] sys_addr; // user access address
- output wire sys_wren; // user write flag
- output wire [31: 0] sys_data_out; // user write data
- output wire sys_rden; // user read flag
- input wire [31: 0] sys_data_in; // user read data
-
-
- //
- // EIM_CLK -> SYS_CLK Request
- //
- wire sys_req; // request pulse in sys_clk clock domain
- wire [50: 0] sys_dout; // transaction data in sys_clk clock domain
-
- cdc_bus_pulse #
- (
- .DATA_WIDTH (51) // {write, read, msb addr, lsb addr, data}
- )
- cdc_eim_sys
- (
- .src_clk (eim_clk),
- .src_din (eim_din),
- .src_req (eim_req),
-
- .dst_clk (sys_clk),
- .dst_dout (sys_dout),
- .dst_pulse (sys_req)
- );
-
-
- //
- // Output Registers
- //
- reg sys_wren_reg = 1'b0; //
- reg sys_rden_reg = 1'b0; //
- reg [16: 0] sys_addr_reg = {17{1'bX}}; //
- reg [31: 0] sys_data_out_reg = {32{1'bX}}; //
-
- assign sys_wren = sys_wren_reg;
- assign sys_rden = sys_rden_reg;
- assign sys_addr = sys_addr_reg;
- assign sys_data_out = sys_data_out_reg;
-
-
- //
- // System (User) Clock Access Handler
- //
- always @(posedge sys_clk)
- //
- if (sys_req) begin // request detected?
- sys_wren_reg <= sys_dout[50]; // set write flag if needed
- sys_rden_reg <= sys_dout[49]; // set read flag if needed
- sys_addr_reg <= sys_dout[48:32]; // set operation address
- sys_data_out_reg <= sys_dout[31: 0]; // set data to write
- end else begin // no request active
- sys_wren_reg <= 1'b0; // clear write flag
- sys_rden_reg <= 1'b0; // clear read flag
- end
-
-
- //
- // System Request 2-cycle delay to compensate registered mux delay in user-side logic
- //
- reg [ 1: 0] sys_req_dly = 2'b00;
-
- always @(posedge sys_clk)
- sys_req_dly <= {sys_req_dly[0], sys_req};
-
-
- //
- // SYS_CLK -> EIM_CLK Acknowledge
- //
- cdc_bus_pulse #
- (
- .DATA_WIDTH (32) // {data}
- )
- cdc_sys_eim
- (
- .src_clk (sys_clk),
- .src_din (sys_data_in),
- .src_req (sys_req_dly[1]),
-
- .dst_clk (eim_clk),
- .dst_dout (eim_dout),
- .dst_pulse (eim_ack)
- );
-
+ (
+ input wire eim_clk, // eim clock
+ input wire eim_req, // eim transaction request
+ output wire eim_ack, // eim transaction acknowledge
+ input wire [50: 0] eim_din, // data from cpu to fpga (write access)
+ output wire [31: 0] eim_dout, // data from fpga to cpu (read access)
+
+ input wire sys_clk, // user internal clock
+ output wire [16: 0] sys_addr, // user access address
+ output wire sys_wren, // user write flag
+ output wire [31: 0] sys_data_out, // user write data
+ output wire sys_rden, // user read flag
+ input wire [31: 0] sys_data_in // user read data
+ );
+
+
+ //
+ // EIM_CLK -> SYS_CLK Request
+ //
+ wire sys_req; // request pulse in sys_clk clock domain
+ wire [50: 0] sys_dout; // transaction data in sys_clk clock domain
+
+ cdc_bus_pulse #
+ (
+ .DATA_WIDTH(51) // {write, read, msb addr, lsb addr, data}
+ )
+ cdc_eim_sys
+ (
+ .src_clk(eim_clk),
+ .src_din(eim_din),
+ .src_req(eim_req),
+
+ .dst_clk(sys_clk),
+ .dst_dout(sys_dout),
+ .dst_pulse(sys_req)
+ );
+
+
+ //
+ // Output Registers
+ //
+ reg sys_wren_reg = 1'b0;
+ reg sys_rden_reg = 1'b0;
+ reg [16: 0] sys_addr_reg = {17{1'bX}};
+ reg [31: 0] sys_data_out_reg = {32{1'bX}};
+
+ assign sys_wren = sys_wren_reg;
+ assign sys_rden = sys_rden_reg;
+ assign sys_addr = sys_addr_reg;
+ assign sys_data_out = sys_data_out_reg;
+
+
+ //
+ // System (User) Clock Access Handler
+ //
+ always @(posedge sys_clk)
+ //
+ if (sys_req) // request detected?
+ begin
+ sys_wren_reg <= sys_dout[50]; // set write flag if needed
+ sys_rden_reg <= sys_dout[49]; // set read flag if needed
+ sys_addr_reg <= sys_dout[48:32]; // set operation address
+ sys_data_out_reg <= sys_dout[31: 0]; // set data to write
+ end
+ else // no request active
+ begin
+ sys_wren_reg <= 1'b0; // clear write flag
+ sys_rden_reg <= 1'b0; // clear read flag
+ end
+
+
+ //
+ // System Request 2-cycle delay to compensate registered mux delay in user-side logic
+ //
+ reg [ 1: 0] sys_req_dly = 2'b00;
+
+ always @(posedge sys_clk)
+ sys_req_dly <= {sys_req_dly[0], sys_req};
+
+
+ //
+ // SYS_CLK -> EIM_CLK Acknowledge
+ //
+ cdc_bus_pulse #
+ (
+ .DATA_WIDTH(32)
+ )
+ cdc_sys_eim
+ (
+ .src_clk(sys_clk),
+ .src_din(sys_data_in),
+ .src_req(sys_req_dly[1]),
+
+ .dst_clk(eim_clk),
+ .dst_dout(eim_dout),
+ .dst_pulse(eim_ack)
+ );
endmodule
diff --git a/rtl/src/verilog/eim_da_phy.v b/rtl/src/verilog/eim_da_phy.v
index 9ef6042..8a4a8d7 100644
--- a/rtl/src/verilog/eim_da_phy.v
+++ b/rtl/src/verilog/eim_da_phy.v
@@ -6,7 +6,7 @@
//
//
// Author: Pavel Shatov
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -37,48 +37,38 @@
//======================================================================
module eim_da_phy
- (
- buf_io,
- buf_di, buf_ro,
- buf_t
- );
+ #(parameter BUS_WIDTH = 16)
+ (
+ inout wire [BUS_WIDTH-1:0] buf_io, // connect directly to top-level pins
+ input wire [BUS_WIDTH-1:0] buf_di, // drive input (value driven onto pins)
+ output wire [BUS_WIDTH-1:0] buf_ro, // receiver output (value read from pins)
+ input wire buf_t // tristate control (driver is disabled during tristate)
+ );
- //
- // Parameters
- //
- parameter BUS_WIDTH = 16;
-
- //
- // Ports
- //
- inout wire [BUS_WIDTH-1:0] buf_io; // connect directly to top-level pins
- input wire [BUS_WIDTH-1:0] buf_di; // drive input (value driven onto pins)
- output wire [BUS_WIDTH-1:0] buf_ro; // receiver output (value read from pins)
- input wire buf_t; // tristate control (driver is disabled during tristate)
-
- //
- // IOBUFs
- //
- genvar i;
- generate for (i=0; i<BUS_WIDTH; i=i+1)
- begin: eim_da
- //
- IOBUF #
- (
- .IOSTANDARD ("LVCMOS33"),
- .DRIVE (12),
- .SLEW ("FAST")
- )
- IOBUF_inst
- (
- .IO (buf_io[i]),
- .O (buf_ro[i]),
- .I (buf_di[i]),
- .T (buf_t)
- );
- //
- end
- endgenerate
+ //
+ // IOBUFs
+ //
+ genvar i;
+ generate
+ for (i = 0; i < BUS_WIDTH; i = i+1)
+ begin: eim_da
+ //
+ IOBUF #
+ (
+ .IOSTANDARD("LVCMOS33"),
+ .DRIVE(12),
+ .SLEW("FAST")
+ )
+ IOBUF_inst
+ (
+ .IO(buf_io[i]),
+ .O(buf_ro[i]),
+ .I(buf_di[i]),
+ .T(buf_t)
+ );
+ //
+ end
+ endgenerate
endmodule
diff --git a/rtl/src/verilog/eim_indicator.v b/rtl/src/verilog/eim_indicator.v
index 56c7190..cf9751d 100644
--- a/rtl/src/verilog/eim_indicator.v
+++ b/rtl/src/verilog/eim_indicator.v
@@ -6,7 +6,7 @@
//
//
// Author: Pavel Shatov
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -37,37 +37,30 @@
//======================================================================
module eim_indicator
- (
- sys_clk, sys_rst,
- eim_active,
- led_out
- );
+ (
+ input wire sys_clk,
+ input wire sys_rst,
+ input wire eim_active,
+ output wire led_out
+ );
- //
- // Ports
- //
- input wire sys_clk;
- input wire sys_rst;
- input wire eim_active;
- output wire led_out;
+ //
+ // Parameters
+ //
+ localparam CNT_BITS = 24; // led will be dim for 2**(24-1) = 8388608 ticks, which is ~100 ms @ 80 MHz.
- //
- // Parameters
- //
- localparam CNT_BITS = 24; // led will be dim for 2**(24-1) = 8388608 ticks, which is ~100 ms @ 80 MHz.
+ //
+ // Counter
+ //
+ reg [CNT_BITS-1:0] cnt;
- //
- // Counter
- //
- reg [CNT_BITS-1:0] cnt;
+ always @(posedge sys_clk)
+ //
+ if (sys_rst) cnt <= {CNT_BITS{1'b0}};
+ else if (cnt > {CNT_BITS{1'b0}}) cnt <= cnt - 1'b1;
+ else if (eim_active) cnt <= {CNT_BITS{1'b1}};
- always @(posedge sys_clk)
- //
- if (sys_rst) cnt <= {CNT_BITS{1'b0}};
- else if (cnt > {CNT_BITS{1'b0}}) cnt <= cnt - 1'b1;
- else if (eim_active) cnt <= {CNT_BITS{1'b1}};
-
- assign led_out = ~cnt[CNT_BITS-1];
+ assign led_out = ~cnt[CNT_BITS-1];
endmodule
diff --git a/rtl/src/verilog/eim_memory.v b/rtl/src/verilog/eim_memory.v
index 5258376..c570ee6 100644
--- a/rtl/src/verilog/eim_memory.v
+++ b/rtl/src/verilog/eim_memory.v
@@ -37,146 +37,146 @@
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
-//======================================================================
-
-module eim_memory
- (
- input wire sys_clk,
- input wire sys_rst,
+//======================================================================
+
+module eim_memory
+ (
+ input wire sys_clk,
+ input wire sys_rst,
+
+ input wire [16: 0] sys_eim_addr,
+ input wire sys_eim_wr,
+ input wire sys_eim_rd,
+ output wire [31: 0] sys_read_data,
+ input wire [31: 0] sys_write_data
+ );
+
+
+ /* Three upper bits of address [16:14] are used to select memory segment.
+ * There can be eight segments. So far segment 0 is used for hashes,
+ * segment 1 is reserved for random number generators, segment 2 is reserved
+ * for chiphers. Other segments are not used so far.
+ */
+
+ /* Every segment has its own memory map, take at look at corresponding
+ * selectors for more information.
+ */
+
+ //----------------------------------------------------------------
+ // Segment Decoder
+ //----------------------------------------------------------------
+ localparam SEGMENT_ADDR_HASHES = 3'd0;
+ localparam SEGMENT_ADDR_RNGS = 3'd1;
+ localparam SEGMENT_ADDR_CIPHERS = 3'd2;
+
+ wire [ 2: 0] addr_segment = sys_eim_addr[16:14]; // 3 upper bits are decoded here
+ wire [13: 0] addr_segment_int = sys_eim_addr[13: 0]; // 14 lower bits are decoded individually
+ // in corresponding segment selectors
+
+ wire [31: 0] segment_hashes_read_data; // data read from HASHES segment
+ wire [31: 0] segment_rngs_read_data; // data read from RNGS segment
+ wire [31: 0] segment_ciphers_read_data; // data read from CIPHERS segment
+
+ wire segment_enable_hashes = (addr_segment == SEGMENT_ADDR_HASHES) ? 1'b1 : 1'b0; // HASHES segment is being addressed
+ wire segment_enable_rngs = (addr_segment == SEGMENT_ADDR_RNGS) ? 1'b1 : 1'b0; // RNGS segment is being addressed
+ wire segment_enable_ciphers = (addr_segment == SEGMENT_ADDR_CIPHERS) ? 1'b1 : 1'b0; // CIPHERS segment is being addressed
+
+
+ //----------------------------------------------------------------
+ // Output (Read Data) Bus
+ //----------------------------------------------------------------
+ reg [31: 0] sys_read_data_reg;
+ assign sys_read_data = sys_read_data_reg;
+
+ always @*
+ //
+ case (addr_segment)
+ SEGMENT_ADDR_HASHES: sys_read_data_reg = segment_hashes_read_data;
+ SEGMENT_ADDR_RNGS: sys_read_data_reg = segment_rngs_read_data;
+ SEGMENT_ADDR_CIPHERS: sys_read_data_reg = segment_ciphers_read_data;
+ default: sys_read_data_reg = {32{1'b0}};
+ endcase
+
+
+
+ //----------------------------------------------------------------
+ // HASH Core Selector
+ //
+ // This selector is used to map core registers into
+ // EIM address space and select which core to send EIM read and
+ // write operations to.
+ //----------------------------------------------------------------
+ core_selector segment_cores
+ (
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst),
+
+ .sys_ena(segment_enable_hashes), // only enable active selector
+
+ .sys_eim_addr(addr_segment_int), // we only connect 14 lower bits of address here,
+ // because we have already decoded 3 upper bits earlier,
+ // every segment can have its own address decoder.
+ .sys_eim_wr(sys_eim_wr),
+ .sys_eim_rd(sys_eim_rd),
+
+ .sys_write_data(sys_write_data),
+ .sys_read_data(segment_hashes_read_data) // output from HASHES segment
+ );
+
+
+ //----------------------------------------------------------------
+ // RNG Selector
+ //
+ // This selector is used to map random number generator registers into
+ // EIM address space and select which RNG to send EIM read and
+ // write operations to. So far there are no RNG cores.
+ //----------------------------------------------------------------
+ rng_selector segment_rngs
+ (
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst),
+
+ .sys_ena(segment_enable_rngs), // only enable active selector
- input wire [16: 0] sys_eim_addr,
- input wire sys_eim_wr,
- input wire sys_eim_rd,
- output wire [31: 0] sys_read_data,
- input wire [31: 0] sys_write_data
- );
-
-
- /* Three upper bits of address [16:14] are used to select memory segment.
- * There can be eight segments. So far segment 0 is used for hashes,
- * segment 1 is reserved for random number generators, segment 2 is reserved
- * for chiphers. Other segments are not used so far.
- */
-
- /* Every segment has its own memory map, take at look at corresponding selectors
- * for more information.
- */
-
- //----------------------------------------------------------------
- // Segment Decoder
- //----------------------------------------------------------------
- localparam SEGMENT_ADDR_HASHES = 3'd0;
- localparam SEGMENT_ADDR_RNGS = 3'd1;
- localparam SEGMENT_ADDR_CIPHERS = 3'd2;
-
- wire [ 2: 0] addr_segment = sys_eim_addr[16:14]; // 3 upper bits are decoded here
- wire [13: 0] addr_segment_int = sys_eim_addr[13: 0]; // 14 lower bits are decoded individually
- // in corresponding segment selectors
-
- wire [31: 0] segment_hashes_read_data; // data read from HASHES segment
- wire [31: 0] segment_rngs_read_data; // data read from RNGS segment
- wire [31: 0] segment_ciphers_read_data; // data read from CIPHERS segment
-
- wire segment_enable_hashes = (addr_segment == SEGMENT_ADDR_HASHES) ? 1'b1 : 1'b0; // HASHES segment is being addressed
- wire segment_enable_rngs = (addr_segment == SEGMENT_ADDR_RNGS) ? 1'b1 : 1'b0; // RNGS segment is being addressed
- wire segment_enable_ciphers = (addr_segment == SEGMENT_ADDR_CIPHERS) ? 1'b1 : 1'b0; // CIPHERS segment is being addressed
-
-
- //----------------------------------------------------------------
- // Output (Read Data) Bus
- //----------------------------------------------------------------
- reg [31: 0] sys_read_data_reg;
- assign sys_read_data = sys_read_data_reg;
-
- always @*
- //
- case (addr_segment)
- SEGMENT_ADDR_HASHES: sys_read_data_reg = segment_hashes_read_data;
- SEGMENT_ADDR_RNGS: sys_read_data_reg = segment_rngs_read_data;
- SEGMENT_ADDR_CIPHERS: sys_read_data_reg = segment_ciphers_read_data;
- default: sys_read_data_reg = {32{1'b0}};
- endcase
-
-
-
- //----------------------------------------------------------------
- // HASH Core Selector
- //
- // This selector is used to map core registers into
- // EIM address space and select which core to send EIM read and
- // write operations to.
- //----------------------------------------------------------------
- core_selector segment_cores
- (
- .sys_clk(sys_clk),
- .sys_rst(sys_rst),
-
- .sys_ena(segment_enable_hashes), // only enable active selector
+ .sys_eim_addr(addr_segment_int), // we only connect 14 lower bits of address here,
+ // because we have already decoded 3 upper bits earlier,
+ // every segment can have its own address decoder.
+ .sys_eim_wr(sys_eim_wr),
+ .sys_eim_rd(sys_eim_rd),
- .sys_eim_addr(addr_segment_int), // we only connect 14 lower bits of address here,
- // because we have already decoded 3 upper bits earlier,
- // every segment can have its own address decoder.
- .sys_eim_wr(sys_eim_wr),
- .sys_eim_rd(sys_eim_rd),
+ .sys_write_data(sys_write_data),
+ .sys_read_data(segment_rngs_read_data) // output from RNGS segment
+ );
+
+
+ //----------------------------------------------------------------
+ // CIPHER Selector
+ //
+ // This selector is used to map cipher registers into
+ // EIM address space and select which CIPHER to send EIM read and
+ // write operations to. So far there are no CIPHER cores.
+ //----------------------------------------------------------------
+ cipher_selector segment_ciphers
+ (
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst),
- .sys_write_data(sys_write_data),
- .sys_read_data(segment_hashes_read_data) // output from HASHES segment
- );
-
-
- //----------------------------------------------------------------
- // RNG Selector
- //
- // This selector is used to map random number generator registers into
- // EIM address space and select which RNG to send EIM read and
- // write operations to. So far there are no RNG cores.
- //----------------------------------------------------------------
- rng_selector segment_rngs
- (
- .sys_clk(sys_clk),
- .sys_rst(sys_rst),
-
- .sys_ena(segment_enable_rngs), // only enable active selector
+ .sys_ena(segment_enable_ciphers), // only enable active selector
- .sys_eim_addr(addr_segment_int), // we only connect 14 lower bits of address here,
- // because we have already decoded 3 upper bits earlier,
- // every segment can have its own address decoder.
- .sys_eim_wr(sys_eim_wr),
- .sys_eim_rd(sys_eim_rd),
+ .sys_eim_addr(addr_segment_int), // we only connect 14 lower bits of address here,
+ // because we have already decoded 3 upper bits earlier,
+ // every segment can have its own address decoder.
+ .sys_eim_wr(sys_eim_wr),
+ .sys_eim_rd(sys_eim_rd),
- .sys_write_data(sys_write_data),
- .sys_read_data(segment_rngs_read_data) // output from RNGS segment
- );
-
-
- //----------------------------------------------------------------
- // CIPHER Selector
- //
- // This selector is used to map cipher registers into
- // EIM address space and select which CIPHER to send EIM read and
- // write operations to. So far there are no CIPHER cores.
- //----------------------------------------------------------------
- cipher_selector segment_ciphers
- (
- .sys_clk(sys_clk),
- .sys_rst(sys_rst),
-
- .sys_ena(segment_enable_ciphers), // only enable active selector
+ .sys_write_data(sys_write_data),
+ .sys_read_data(segment_ciphers_read_data) // output from CIPHERS segment
+ );
+
+
+endmodule
- .sys_eim_addr(addr_segment_int), // we only connect 14 lower bits of address here,
- // because we have already decoded 3 upper bits earlier,
- // every segment can have its own address decoder.
- .sys_eim_wr(sys_eim_wr),
- .sys_eim_rd(sys_eim_rd),
- .sys_write_data(sys_write_data),
- .sys_read_data(segment_ciphers_read_data) // output from CIPHERS segment
- );
-
-
-endmodule
-
-
//======================================================================
// EOF eim_memory.v
//======================================================================
diff --git a/rtl/src/verilog/novena_baseline_top.v b/rtl/src/verilog/novena_baseline_top.v
index cc9e5e7..3499fa3 100644
--- a/rtl/src/verilog/novena_baseline_top.v
+++ b/rtl/src/verilog/novena_baseline_top.v
@@ -8,7 +8,7 @@
//
//
// Author: Pavel Shatov
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -39,147 +39,147 @@
//======================================================================
module novena_baseline_top
- (
- // Differential input for 50 MHz general clock.
- input wire gclk_p_pin,
- input wire gclk_n_pin,
-
- // Reset controlled by the CPU.
- // this must be configured as input w/pullup
- input wire reset_mcu_b_pin,
-
- // Cryptech avalanche noise board input and LED outputs
- input wire ct_noise,
- output wire [07 : 0] ct_led,
-
- // EIM interface
- input wire eim_bclk, // EIM burst clock. Started by the CPU.
- input wire eim_cs0_n, // Chip select (active low).
- inout wire [15 : 0] eim_da, // Bidirectional address and data port.
- input wire [18: 16] eim_a, // MSB part of address port.
- input wire eim_lba_n, // Latch address signal (active low).
- input wire eim_wr_n, // write enable signal (active low).
- input wire eim_oe_n, // output enable signal (active low).
- output wire eim_wait_n, // Data wait signal (active low).
-
- // Novena utility ports
- apoptosis_pin, // Hold low to not restart after config.
- led_pin // LED on edge close to the FPGA.
- );
-
-
- //----------------------------------------------------------------
- // Clock Manager
- //
- // Clock manager is used to buffer BCLK, generate SYS_CLK
- // from GCLK and implement the reset logic.
- //----------------------------------------------------------------
- wire sys_clk;
- wire sys_rst;
- wire eim_bclk_buf;
-
- novena_clkmgr clkmgr
- (
- .gclk_p(gclk_p_pin),
- .gclk_n(gclk_n_pin),
-
- .reset_mcu_b(reset_mcu_b_pin),
-
- .sys_clk(sys_clk),
- .sys_rst(sys_rst),
-
- .bclk_in(eim_bclk),
- .bclk_out(eim_bclk_buf)
- );
-
-
- //----------------------------------------------------------------
- // EIM Arbiter
- //
- // EIM arbiter handles EIM access and transfers it into
- // `sys_clk' clock domain.
- //----------------------------------------------------------------
- wire [16: 0] sys_eim_addr;
- wire sys_eim_wr;
- wire sys_eim_rd;
- wire [31: 0] sys_eim_dout;
- wire [31: 0] sys_eim_din;
-
- eim_arbiter eim
- (
- .eim_bclk(eim_bclk_buf),
- .eim_cs0_n(eim_cs0_n),
- .eim_da(eim_da),
- .eim_a(eim_a),
- .eim_lba_n(eim_lba_n),
- .eim_wr_n(eim_wr_n),
- .eim_oe_n(eim_oe_n),
- .eim_wait_n(eim_wait_n),
-
- .sys_clk(sys_clk),
-
- .sys_addr(sys_eim_addr),
- .sys_wren(sys_eim_wr),
- .sys_data_out(sys_eim_dout),
- .sys_rden(sys_eim_rd),
- .sys_data_in(sys_eim_din)
- );
-
-
- //----------------------------------------------------------------
- // Memory Mapper
- //
- // This multiplexer is used to map different types of cores, such as
- // hashes, RNGs and ciphers to different regions (segments) of memory.
- //----------------------------------------------------------------
- eim_memory mem
- (
- .sys_clk(sys_clk),
- .sys_rst(sys_rst),
-
- .sys_eim_addr(sys_eim_addr),
- .sys_eim_wr(sys_eim_wr),
- .sys_eim_rd(sys_eim_rd),
-
- .sys_write_data(sys_eim_dout),
- .sys_read_data(sys_eim_din)
- );
-
-
- //----------------------------------------------------------------
- // LED Driver
- //
- // A simple utility LED driver that turns on the Novena
- // board LED when the EIM interface is active.
- //----------------------------------------------------------------
- eim_indicator led
- (
- .sys_clk(sys_clk),
- .sys_rst(sys_rst),
- .eim_active(sys_eim_wr | sys_eim_rd),
- .led_out(led_pin)
- );
-
-
- //----------------------------------------------------------------
- // Cryptech Logic
- //
- // Logic specific to the Cryptech use of the Novena.
- // Currently we just hard wire the LED outputs.
- //----------------------------------------------------------------
- assign ct_led = {8{ct_noise}};
-
-
- //----------------------------------------------------------------
- // Novena Patch
- //
- // Patch logic to keep the Novena board happy.
- // The apoptosis_pin pin must be kept low or the whole board
- // (more exactly the CPU) will be reset after the FPGA has
- // been configured.
- //----------------------------------------------------------------
- assign apoptosis_pin = 1'b0;
-
+ (
+ // Differential input for 50 MHz general clock.
+ input wire gclk_p_pin,
+ input wire gclk_n_pin,
+
+ // Reset controlled by the CPU.
+ // this must be configured as input w/pullup
+ input wire reset_mcu_b_pin,
+
+ // Cryptech avalanche noise board input and LED outputs
+ input wire ct_noise,
+ output wire [7 : 0] ct_led,
+
+ // EIM interface
+ input wire eim_bclk, // EIM burst clock. Started by the CPU.
+ input wire eim_cs0_n, // Chip select (active low).
+ inout wire [15 : 0] eim_da, // Bidirectional address and data port.
+ input wire [18: 16] eim_a, // MSB part of address port.
+ input wire eim_lba_n, // Latch address signal (active low).
+ input wire eim_wr_n, // write enable signal (active low).
+ input wire eim_oe_n, // output enable signal (active low).
+ output wire eim_wait_n, // Data wait signal (active low).
+
+ // Novena utility ports
+ apoptosis_pin, // Hold low to not restart after config.
+ led_pin // LED on edge close to the FPGA.
+ );
+
+
+ //----------------------------------------------------------------
+ // Clock Manager
+ //
+ // Clock manager is used to buffer BCLK, generate SYS_CLK
+ // from GCLK and implement the reset logic.
+ //----------------------------------------------------------------
+ wire sys_clk;
+ wire sys_rst;
+ wire eim_bclk_buf;
+
+ novena_clkmgr clkmgr
+ (
+ .gclk_p(gclk_p_pin),
+ .gclk_n(gclk_n_pin),
+
+ .reset_mcu_b(reset_mcu_b_pin),
+
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst),
+
+ .bclk_in(eim_bclk),
+ .bclk_out(eim_bclk_buf)
+ );
+
+
+ //----------------------------------------------------------------
+ // EIM Arbiter
+ //
+ // EIM arbiter handles EIM access and transfers it into
+ // `sys_clk' clock domain.
+ //----------------------------------------------------------------
+ wire [16: 0] sys_eim_addr;
+ wire sys_eim_wr;
+ wire sys_eim_rd;
+ wire [31: 0] sys_eim_dout;
+ wire [31: 0] sys_eim_din;
+
+ eim_arbiter eim
+ (
+ .eim_bclk(eim_bclk_buf),
+ .eim_cs0_n(eim_cs0_n),
+ .eim_da(eim_da),
+ .eim_a(eim_a),
+ .eim_lba_n(eim_lba_n),
+ .eim_wr_n(eim_wr_n),
+ .eim_oe_n(eim_oe_n),
+ .eim_wait_n(eim_wait_n),
+
+ .sys_clk(sys_clk),
+
+ .sys_addr(sys_eim_addr),
+ .sys_wren(sys_eim_wr),
+ .sys_data_out(sys_eim_dout),
+ .sys_rden(sys_eim_rd),
+ .sys_data_in(sys_eim_din)
+ );
+
+
+ //----------------------------------------------------------------
+ // Memory Mapper
+ //
+ // This multiplexer is used to map different types of cores, such as
+ // hashes, RNGs and ciphers to different regions (segments) of memory.
+ //----------------------------------------------------------------
+ eim_memory mem
+ (
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst),
+
+ .sys_eim_addr(sys_eim_addr),
+ .sys_eim_wr(sys_eim_wr),
+ .sys_eim_rd(sys_eim_rd),
+
+ .sys_write_data(sys_eim_dout),
+ .sys_read_data(sys_eim_din)
+ );
+
+
+ //----------------------------------------------------------------
+ // LED Driver
+ //
+ // A simple utility LED driver that turns on the Novena
+ // board LED when the EIM interface is active.
+ //----------------------------------------------------------------
+ eim_indicator led
+ (
+ .sys_clk(sys_clk),
+ .sys_rst(sys_rst),
+ .eim_active(sys_eim_wr | sys_eim_rd),
+ .led_out(led_pin)
+ );
+
+
+ //----------------------------------------------------------------
+ // Cryptech Logic
+ //
+ // Logic specific to the Cryptech use of the Novena.
+ // Currently we just hard wire the LED outputs.
+ //----------------------------------------------------------------
+ assign ct_led = {8{ct_noise}};
+
+
+ //----------------------------------------------------------------
+ // Novena Patch
+ //
+ // Patch logic to keep the Novena board happy.
+ // The apoptosis_pin pin must be kept low or the whole board
+ // (more exactly the CPU) will be reset after the FPGA has
+ // been configured.
+ //----------------------------------------------------------------
+ assign apoptosis_pin = 1'b0;
+
endmodule
diff --git a/rtl/src/verilog/novena_clkmgr.v b/rtl/src/verilog/novena_clkmgr.v
index c68cb43..00b2e5b 100644
--- a/rtl/src/verilog/novena_clkmgr.v
+++ b/rtl/src/verilog/novena_clkmgr.v
@@ -7,7 +7,7 @@
//
//
// Author: Pavel Shatov
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -38,100 +38,102 @@
//======================================================================
module novena_clkmgr
- (
- gclk_p, gclk_n,
- reset_mcu_b,
- sys_clk, sys_rst,
- bclk_in, bclk_out
- );
+ (
+ input wire gclk_p, // signal from clock pins
+ input wire gclk_n, //
- //
- // Ports
- //
- input wire gclk_p; // signal from clock pins
- input wire gclk_n; //
+ input wire reset_mcu_b, // cpu reset (async)
- input wire reset_mcu_b; // cpu reset (async)
+ output wire sys_clk, // buffered system clock output
+ output wire sys_rst, // system reset output (sync)
- output wire sys_clk; // buffered system clock output
- output wire sys_rst; // system reset output (sync)
+ input wire bclk_in, // signal from clock pin
+ output wire bclk_out // buffered clock output
+ );
- input wire bclk_in; // signal from clock pin
- output wire bclk_out; // buffered clock output
+ //
+ // Ports
+ //
- //
- // IBUFGDS
- //
- (* BUFFER_TYPE="NONE" *)
- wire gclk;
+ //
+ // IBUFGDS
+ //
+ (* BUFFER_TYPE="NONE" *)
+ wire gclk;
- IBUFGDS IBUFGDS_gclk
- (
- .I (gclk_p),
- .IB (gclk_n),
- .O (gclk)
- );
+ IBUFGDS IBUFGDS_gclk
+ (
+ .I(gclk_p),
+ .IB(gclk_n),
+ .O(gclk)
+ );
- //
- // DCM
- //
- wire dcm_reset; // dcm reset
- wire dcm_locked; // output clock valid
- wire gclk_missing; // no input clock
+ //
+ // DCM
+ //
+ wire dcm_reset; // dcm reset
+ wire dcm_locked; // output clock valid
+ wire gclk_missing; // no input clock
- clkmgr_dcm dcm
- (
- .CLK_IN1 (gclk),
- .RESET (dcm_reset),
- .INPUT_CLK_STOPPED (gclk_missing),
+ clkmgr_dcm dcm
+ (
+ .CLK_IN1(gclk),
+ .RESET(dcm_reset),
+ .INPUT_CLK_STOPPED(gclk_missing),
- .CLK_OUT1 (sys_clk),
- .CLK_VALID (dcm_locked)
- );
+ .CLK_OUT1(sys_clk),
+ .CLK_VALID(dcm_locked)
+ );
- //
- // DCM Reset Logic
- //
+ //
+ // DCM Reset Logic
+ //
- /* DCM should be reset on power-up, when input clock is stopped or when the CPU gets reset. */
+ /* DCM should be reset on power-up, when input clock is stopped or when the
+ * CPU gets reset.
+ */
- reg [15: 0] dcm_rst_shreg = {16{1'b1}}; // 16-bit shift register
+ reg [15: 0] dcm_rst_shreg = {16{1'b1}}; // 16-bit shift register
- always @(posedge gclk or negedge reset_mcu_b or posedge gclk_missing)
- //
- if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1)) dcm_rst_shreg <= {16{1'b1}};
- else dcm_rst_shreg <= {dcm_rst_shreg[14:0], 1'b0};
+ always @(posedge gclk or negedge reset_mcu_b or posedge gclk_missing)
+ //
+ if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1))
+ dcm_rst_shreg <= {16{1'b1}};
+ else
+ dcm_rst_shreg <= {dcm_rst_shreg[14:0], 1'b0};
- assign dcm_reset = dcm_rst_shreg[15];
+ assign dcm_reset = dcm_rst_shreg[15];
- //
- // System Reset Logic
- //
+ //
+ // System Reset Logic
+ //
- /* System reset is asserted for 16 cycles whenever DCM aquires lock. */
+ /* System reset is asserted for 16 cycles whenever DCM aquires lock. */
- reg [15: 0] sys_rst_shreg = {16{1'b1}}; // 16-bit shift register
+ reg [15: 0] sys_rst_shreg = {16{1'b1}}; // 16-bit shift register
- always @(posedge sys_clk or negedge reset_mcu_b or posedge gclk_missing or negedge dcm_locked)
- //
- if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1) || (dcm_locked == 1'b0)) sys_rst_shreg <= {16{1'b1}};
- else if (dcm_locked == 1'b1) sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b0};
+ always @(posedge sys_clk or negedge reset_mcu_b or posedge gclk_missing or negedge dcm_locked)
+ //
+ if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1) || (dcm_locked == 1'b0))
+ sys_rst_shreg <= {16{1'b1}};
+ else if (dcm_locked == 1'b1)
+ sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b0};
- assign sys_rst = sys_rst_shreg[15];
+ assign sys_rst = sys_rst_shreg[15];
- //
- // BCLK BUFG
- //
- BUFG BUFG_BCLK
- (
- .I (bclk_in),
- .O (bclk_out)
- );
+ //
+ // BCLK BUFG
+ //
+ BUFG BUFG_BCLK
+ (
+ .I(bclk_in),
+ .O(bclk_out)
+ );
endmodule
diff --git a/rtl/src/verilog/novena_regs.v b/rtl/src/verilog/novena_regs.v
index 88b35ab..7341092 100644
--- a/rtl/src/verilog/novena_regs.v
+++ b/rtl/src/verilog/novena_regs.v
@@ -1,80 +1,126 @@
-`timescale 1ns / 1ps
-
-module novena_regs
- (
- input wire clk,
- input wire rst,
+//======================================================================
+//
+// novena_regs.v
+// -------------
+// Global registers for the Cryptech Novena FPGA framework.
+//
+//
+// Author: Pavel Shatov
+// Copyright (c) 2015, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
- input wire cs,
- input wire we,
+`timescale 1ns / 1ps
- input wire [ 7 : 0] address,
- input wire [31 : 0] write_data,
- output wire [31 : 0] read_data
- );
-
-
- //----------------------------------------------------------------
- // Board-Level Registers
- //----------------------------------------------------------------
- localparam ADDR_BOARD_TYPE = 8'h00; // board id
- localparam ADDR_FIRMWARE_VER = 8'h01; // bitstream version
- localparam ADDR_DUMMY_REG = 8'hFF; // general-purpose register
-
-
- //----------------------------------------------------------------
- // Constants
- //----------------------------------------------------------------
- localparam NOVENA_BOARD_TYPE = 32'h50565431; // PVT1
- localparam NOVENA_DESIGN_VER = 32'h00_01_00_0b; // v0.1.0b
+module novena_regs
+ (
+ input wire clk,
+ input wire rst,
+ input wire cs,
+ input wire we,
- //
- // Output Register
- //
- reg [31: 0] tmp_read_data;
- assign read_data = tmp_read_data;
-
-
- /* This dummy register can be used by users to check that they can actually write something.
- */
-
- reg [31: 0] reg_dummy;
-
-
- //
- // Access Handler
- //
- always @(posedge clk)
- //
- if (rst) reg_dummy <= {32{1'b0}};
- else if (cs) begin
- //
- if (we) begin
- //
- // WRITE handler
- //
- case (address)
- ADDR_DUMMY_REG: reg_dummy <= write_data;
- endcase
- //
- end else begin
- //
- // READ handler
- //
- case (address)
- ADDR_BOARD_TYPE: tmp_read_data <= NOVENA_BOARD_TYPE;
- ADDR_FIRMWARE_VER: tmp_read_data <= NOVENA_DESIGN_VER;
- ADDR_DUMMY_REG: tmp_read_data <= reg_dummy;
- //
- default: tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
- /*
- default: tmp_read_data <= {32{1'bX}}; // don't care what to read from non-existent locations
- */
- endcase
- //
- end
- //
- end
-
-endmodule
+ input wire [ 7 : 0] address,
+ input wire [31 : 0] write_data,
+ output wire [31 : 0] read_data
+ );
+
+
+ //----------------------------------------------------------------
+ // Board-Level Registers
+ //----------------------------------------------------------------
+ localparam ADDR_BOARD_TYPE = 8'h00; // board id
+ localparam ADDR_FIRMWARE_VER = 8'h01; // bitstream version
+ localparam ADDR_DUMMY_REG = 8'hFF; // general-purpose register
+
+
+ //----------------------------------------------------------------
+ // Constants
+ //----------------------------------------------------------------
+ localparam NOVENA_BOARD_TYPE = 32'h50565431; // PVT1
+ localparam NOVENA_DESIGN_VER = 32'h00_01_00_0b; // v0.1.0b
+
+
+ //
+ // Output Register
+ //
+ reg [31: 0] tmp_read_data;
+ assign read_data = tmp_read_data;
+
+
+ /* This dummy register can be used by users to check that they can actually
+ * write something.
+ */
+
+ reg [31: 0] reg_dummy;
+
+
+ //
+ // Access Handler
+ //
+ always @(posedge clk)
+ //
+ if (rst)
+ reg_dummy <= {32{1'b0}};
+ else if (cs) begin
+ //
+ if (we) begin
+ //
+ // WRITE handler
+ //
+ case (address)
+ ADDR_DUMMY_REG:
+ reg_dummy <= write_data;
+ endcase
+ //
+ end else begin
+ //
+ // READ handler
+ //
+ case (address)
+ ADDR_BOARD_TYPE:
+ tmp_read_data <= NOVENA_BOARD_TYPE;
+ ADDR_FIRMWARE_VER:
+ tmp_read_data <= NOVENA_DESIGN_VER;
+ ADDR_DUMMY_REG:
+ tmp_read_data <= reg_dummy;
+ //
+ default:
+ tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
+ endcase
+ //
+ end
+ //
+ end
+
+endmodule
+
+//======================================================================
+// EOF novena_regs.v
+//======================================================================
diff --git a/rtl/src/verilog/rng_selector.v b/rtl/src/verilog/rng_selector.v
index 7a1fe7c..f86b3e9 100644
--- a/rtl/src/verilog/rng_selector.v
+++ b/rtl/src/verilog/rng_selector.v
@@ -40,72 +40,70 @@
//======================================================================
module rng_selector
- (
- input wire sys_clk,
- input wire sys_rst,
- input wire sys_ena,
+ (
+ input wire sys_clk,
+ input wire sys_rst,
+ input wire sys_ena,
- input wire [13: 0] sys_eim_addr,
- input wire sys_eim_wr,
- input wire sys_eim_rd,
- output wire [31 : 0] sys_read_data,
- input wire [31 : 0] sys_write_data
- );
-
-
- //
- // Output Register
- //
- reg [31: 0] tmp_read_data;
- assign sys_read_data = tmp_read_data;
-
-
- /* So far we have no RNG cores, let's make some dummy 32-bit registers here
- * to prevent ISE from complaining that we don't use input ports.
- */
-
- reg [31: 0] reg_dummy_first;
- reg [31: 0] reg_dummy_second;
- reg [31: 0] reg_dummy_third;
-
- always @(posedge sys_clk)
- //
- if (sys_rst) begin
- reg_dummy_first <= {8{4'hA}};
- reg_dummy_second <= {8{4'hB}};
- reg_dummy_third <= {8{4'hC}};
- end else if (sys_ena) begin
- //
- if (sys_eim_wr) begin
- //
- // WRITE handler
- //
- case (sys_eim_addr)
- 14'd0: reg_dummy_first <= sys_write_data;
- 14'd1: reg_dummy_second <= sys_write_data;
- 14'd2: reg_dummy_third <= sys_write_data;
- endcase
- //
- end
- //
- if (sys_eim_rd) begin
- //
- // READ handler
- //
- case (sys_eim_addr)
- 14'd0: tmp_read_data <= reg_dummy_first;
- 14'd1: tmp_read_data <= reg_dummy_second;
- 14'd2: tmp_read_data <= reg_dummy_third;
- //
- default: tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
- /*
- default: tmp_read_data <= {32{1'bX}}; // don't care what to read from non-existent locations
- */
- endcase
- //
- end
- //
- end
+ input wire [13: 0] sys_eim_addr,
+ input wire sys_eim_wr,
+ input wire sys_eim_rd,
+ output wire [31 : 0] sys_read_data,
+ input wire [31 : 0] sys_write_data
+ );
+
+
+ //
+ // Output Register
+ //
+ reg [31: 0] tmp_read_data;
+ assign sys_read_data = tmp_read_data;
+
+
+ /* So far we have no RNG cores, let's make some dummy 32-bit registers here
+ * to prevent ISE from complaining that we don't use input ports.
+ */
+
+ reg [31: 0] reg_dummy_first;
+ reg [31: 0] reg_dummy_second;
+ reg [31: 0] reg_dummy_third;
+
+ always @(posedge sys_clk)
+ //
+ if (sys_rst) begin
+ reg_dummy_first <= {8{4'hA}};
+ reg_dummy_second <= {8{4'hB}};
+ reg_dummy_third <= {8{4'hC}};
+ end else if (sys_ena) begin
+ //
+ if (sys_eim_wr) begin
+ //
+ // WRITE handler
+ //
+ case (sys_eim_addr)
+ 14'd0: reg_dummy_first <= sys_write_data;
+ 14'd1: reg_dummy_second <= sys_write_data;
+ 14'd2: reg_dummy_third <= sys_write_data;
+ endcase
+ //
+ end
+ //
+ if (sys_eim_rd) begin
+ //
+ // READ handler
+ //
+ case (sys_eim_addr)
+ 14'd0: tmp_read_data <= reg_dummy_first;
+ 14'd1: tmp_read_data <= reg_dummy_second;
+ 14'd2: tmp_read_data <= reg_dummy_third;
+ //
+ default:
+ tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
+ endcase
+ //
+ end
+ //
+ end
endmodule
diff --git a/rtl/src/verilog/sha1.v b/rtl/src/verilog/sha1.v
index 2595132..d0b4a4e 100644
--- a/rtl/src/verilog/sha1.v
+++ b/rtl/src/verilog/sha1.v
@@ -6,7 +6,7 @@
// a simple memory like interface with 32 bit data access.
//
// Authors: Joachim Strömbergson, Paul Selkirk
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
@@ -38,15 +38,15 @@
module sha1(
// Clock and reset.
- input wire clk,
- input wire reset_n,
+ input wire clk,
+ input wire reset_n,
// Control.
- input wire cs,
- input wire we,
+ input wire cs,
+ input wire we,
// Data ports.
- input wire [7 : 0] address,
+ input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
@@ -87,8 +87,8 @@ module sha1(
reg init_reg;
reg next_reg;
- reg [31 : 0] tmp_read_data;
- reg [31 : 0] tmp_read_data_reg;
+ reg [31 : 0] tmp_read_data;
+ reg [31 : 0] tmp_read_data_reg;
//----------------------------------------------------------------
// Wires.
@@ -150,55 +150,55 @@ module sha1(
//----------------------------------------------------------------
always @(posedge clk)
begin
- init_reg <= 0;
- next_reg <= 0;
-
- if (cs && we)
- begin
- // write operations
- if ((address >= ADDR_BLOCK) &&
- (address < ADDR_BLOCK + BLOCK_WORDS))
- block_reg[((address - ADDR_BLOCK) * 32)+:32] <= write_data;
- else if (address == ADDR_CTRL)
- begin
- init_reg <= write_data[CTRL_INIT_BIT];
- next_reg <= write_data[CTRL_NEXT_BIT];
- end
- end
+ init_reg <= 0;
+ next_reg <= 0;
+
+ if (cs && we)
+ begin
+ // write operations
+ if ((address >= ADDR_BLOCK) &&
+ (address < ADDR_BLOCK + BLOCK_WORDS))
+ block_reg[((address - ADDR_BLOCK) * 32)+:32] <= write_data;
+ else if (address == ADDR_CTRL)
+ begin
+ init_reg <= write_data[CTRL_INIT_BIT];
+ next_reg <= write_data[CTRL_NEXT_BIT];
+ end
+ end
end
always @*
begin
- tmp_read_data = 32'h00000000;
-
- if (cs && !we)
- begin
- // read operations
- if ((address >= ADDR_BLOCK) &&
- (address < ADDR_BLOCK + BLOCK_WORDS))
- tmp_read_data = block_reg[((address - ADDR_BLOCK) * 32)+:32];
- else if ((address >= ADDR_DIGEST) &&
- (address < ADDR_DIGEST + DIGEST_WORDS))
- tmp_read_data = digest_reg[((address - ADDR_DIGEST) * 32)+:32];
- else
- case (address)
- ADDR_NAME0:
- tmp_read_data = core_name0;
- ADDR_NAME1:
- tmp_read_data = core_name1;
- ADDR_VERSION:
- tmp_read_data = core_version;
- ADDR_CTRL:
- tmp_read_data = core_ctrl;
- ADDR_STATUS:
- tmp_read_data = core_status;
- endcase
- end
+ tmp_read_data = 32'h00000000;
+
+ if (cs && !we)
+ begin
+ // read operations
+ if ((address >= ADDR_BLOCK) &&
+ (address < ADDR_BLOCK + BLOCK_WORDS))
+ tmp_read_data = block_reg[((address - ADDR_BLOCK) * 32)+:32];
+ else if ((address >= ADDR_DIGEST) &&
+ (address < ADDR_DIGEST + DIGEST_WORDS))
+ tmp_read_data = digest_reg[((address - ADDR_DIGEST) * 32)+:32];
+ else
+ case (address)
+ ADDR_NAME0:
+ tmp_read_data = core_name0;
+ ADDR_NAME1:
+ tmp_read_data = core_name1;
+ ADDR_VERSION:
+ tmp_read_data = core_version;
+ ADDR_CTRL:
+ tmp_read_data = core_ctrl;
+ ADDR_STATUS:
+ tmp_read_data = core_status;
+ endcase
+ end
end
always @(posedge clk)
begin
- tmp_read_data_reg <= tmp_read_data;
+ tmp_read_data_reg <= tmp_read_data;
end
endmodule // sha1
diff --git a/rtl/src/verilog/sha256.v b/rtl/src/verilog/sha256.v
index d6fb133..04048b1 100644
--- a/rtl/src/verilog/sha256.v
+++ b/rtl/src/verilog/sha256.v
@@ -6,7 +6,7 @@
// a simple memory like interface with 32 bit data access.
//
// Authors: Joachim Strömbergson, Paul Selkirk
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
@@ -38,15 +38,15 @@
module sha256(
// Clock and reset.
- input wire clk,
- input wire reset_n,
+ input wire clk,
+ input wire reset_n,
// Control.
- input wire cs,
- input wire we,
+ input wire cs,
+ input wire we,
// Data ports.
- input wire [7 : 0] address,
+ input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
@@ -87,8 +87,8 @@ module sha256(
reg init_reg;
reg next_reg;
- reg [31 : 0] tmp_read_data;
- reg [31 : 0] tmp_read_data_reg;
+ reg [31 : 0] tmp_read_data;
+ reg [31 : 0] tmp_read_data_reg;
//----------------------------------------------------------------
// Wires.
@@ -150,55 +150,55 @@ module sha256(
//----------------------------------------------------------------
always @(posedge clk)
begin
- init_reg <= 0;
- next_reg <= 0;
-
- if (cs && we)
- begin
- // write operations
- if ((address >= ADDR_BLOCK) &&
- (address < ADDR_BLOCK + BLOCK_WORDS))
- block_reg[((address - ADDR_BLOCK) * 32)+:32] <= write_data;
- else if (address == ADDR_CTRL)
- begin
- init_reg <= write_data[CTRL_INIT_BIT];
- next_reg <= write_data[CTRL_NEXT_BIT];
- end
- end
+ init_reg <= 0;
+ next_reg <= 0;
+
+ if (cs && we)
+ begin
+ // write operations
+ if ((address >= ADDR_BLOCK) &&
+ (address < ADDR_BLOCK + BLOCK_WORDS))
+ block_reg[((address - ADDR_BLOCK) * 32)+:32] <= write_data;
+ else if (address == ADDR_CTRL)
+ begin
+ init_reg <= write_data[CTRL_INIT_BIT];
+ next_reg <= write_data[CTRL_NEXT_BIT];
+ end
+ end
end
always @*
begin
- tmp_read_data = 32'h00000000;
-
- if (cs && !we)
- begin
- // read operations
- if ((address >= ADDR_BLOCK) &&
- (address < ADDR_BLOCK + BLOCK_WORDS))
- tmp_read_data = block_reg[((address - ADDR_BLOCK) * 32)+:32];
- else if ((address >= ADDR_DIGEST) &&
- (address < ADDR_DIGEST + DIGEST_WORDS))
- tmp_read_data = digest_reg[((address - ADDR_DIGEST) * 32)+:32];
- else
- case (address)
- ADDR_NAME0:
- tmp_read_data = core_name0;
- ADDR_NAME1:
- tmp_read_data = core_name1;
- ADDR_VERSION:
- tmp_read_data = core_version;
- ADDR_CTRL:
- tmp_read_data = core_ctrl;
- ADDR_STATUS:
- tmp_read_data = core_status;
- endcase
- end
+ tmp_read_data = 32'h00000000;
+
+ if (cs && !we)
+ begin
+ // read operations
+ if ((address >= ADDR_BLOCK) &&
+ (address < ADDR_BLOCK + BLOCK_WORDS))
+ tmp_read_data = block_reg[((address - ADDR_BLOCK) * 32)+:32];
+ else if ((address >= ADDR_DIGEST) &&
+ (address < ADDR_DIGEST + DIGEST_WORDS))
+ tmp_read_data = digest_reg[((address - ADDR_DIGEST) * 32)+:32];
+ else
+ case (address)
+ ADDR_NAME0:
+ tmp_read_data = core_name0;
+ ADDR_NAME1:
+ tmp_read_data = core_name1;
+ ADDR_VERSION:
+ tmp_read_data = core_version;
+ ADDR_CTRL:
+ tmp_read_data = core_ctrl;
+ ADDR_STATUS:
+ tmp_read_data = core_status;
+ endcase
+ end
end
always @(posedge clk)
begin
- tmp_read_data_reg <= tmp_read_data;
+ tmp_read_data_reg <= tmp_read_data;
end
endmodule // sha256
diff --git a/rtl/src/verilog/sha512.v b/rtl/src/verilog/sha512.v
index 4d2a9e7..8826782 100644
--- a/rtl/src/verilog/sha512.v
+++ b/rtl/src/verilog/sha512.v
@@ -6,7 +6,7 @@
// a simple memory like interface with 32 bit data access.
//
// Authors: Joachim Strömbergson, Paul Selkirk
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
@@ -38,15 +38,15 @@
module sha512(
// Clock and reset.
- input wire clk,
- input wire reset_n,
+ input wire clk,
+ input wire reset_n,
// Control.
- input wire cs,
- input wire we,
+ input wire cs,
+ input wire we,
// Data ports.
- input wire [7 : 0] address,
+ input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
@@ -98,12 +98,12 @@ module sha512(
reg [0 : DIGEST_BITS - 1] digest_reg;
reg init_reg;
reg next_reg;
- reg [1 : 0] mode_reg;
- reg work_factor_reg;
- reg [31 : 0] work_factor_num_reg;
+ reg [1 : 0] mode_reg;
+ reg work_factor_reg;
+ reg [31 : 0] work_factor_num_reg;
- reg [31 : 0] tmp_read_data;
- reg [31 : 0] tmp_read_data_reg;
+ reg [31 : 0] tmp_read_data;
+ reg [31 : 0] tmp_read_data_reg;
//----------------------------------------------------------------
// Wires.
@@ -111,9 +111,9 @@ module sha512(
wire core_init;
wire core_next;
wire core_ready;
- wire [1 : 0] core_mode;
- wire core_work_factor;
- wire [31 : 0] core_work_factor_num;
+ wire [1 : 0] core_mode;
+ wire core_work_factor;
+ wire [31 : 0] core_work_factor_num;
wire [0 : BLOCK_BITS - 1] core_block;
wire [0 : DIGEST_BITS - 1] core_digest;
wire core_digest_valid;
@@ -176,66 +176,66 @@ module sha512(
//----------------------------------------------------------------
always @(posedge clk)
begin
- init_reg <= 0;
- next_reg <= 0;
+ init_reg <= 0;
+ next_reg <= 0;
mode_reg <= MODE_SHA_512;
work_factor_reg <= 0;
work_factor_num_reg <= DEFAULT_WORK_FACTOR_NUM;
- if (cs && we)
- begin
- // write operations
- if ((address >= ADDR_BLOCK) &&
- (address < ADDR_BLOCK + BLOCK_WORDS))
- block_reg[((address - ADDR_BLOCK) * 32)+:32] <= write_data;
- else if (address == ADDR_CTRL)
- begin
- init_reg <= write_data[CTRL_INIT_BIT];
- next_reg <= write_data[CTRL_NEXT_BIT];
+ if (cs && we)
+ begin
+ // write operations
+ if ((address >= ADDR_BLOCK) &&
+ (address < ADDR_BLOCK + BLOCK_WORDS))
+ block_reg[((address - ADDR_BLOCK) * 32)+:32] <= write_data;
+ else if (address == ADDR_CTRL)
+ begin
+ init_reg <= write_data[CTRL_INIT_BIT];
+ next_reg <= write_data[CTRL_NEXT_BIT];
mode_reg <= write_data[CTRL_MODE_HIGH_BIT : CTRL_MODE_LOW_BIT];
work_factor_reg <= write_data[CTRL_WORK_FACTOR_BIT];
- end
- else if (address == ADDR_WORK_FACTOR_NUM)
- begin
- work_factor_num_reg <= write_data;
- end
- end
+ end
+ else if (address == ADDR_WORK_FACTOR_NUM)
+ begin
+ work_factor_num_reg <= write_data;
+ end
+ end
end
always @*
begin
- tmp_read_data = 32'h00000000;
-
- if (cs && !we)
- begin
- // read operations
- if ((address >= ADDR_BLOCK) &&
- (address < ADDR_BLOCK + BLOCK_WORDS))
- tmp_read_data = block_reg[((address - ADDR_BLOCK) * 32)+:32];
- else if ((address >= ADDR_DIGEST) &&
- (address < ADDR_DIGEST + DIGEST_WORDS))
- tmp_read_data = digest_reg[((address - ADDR_DIGEST) * 32)+:32];
- else
- case (address)
- ADDR_NAME0:
- tmp_read_data = core_name0;
- ADDR_NAME1:
- tmp_read_data = core_name1;
- ADDR_VERSION:
- tmp_read_data = core_version;
- ADDR_CTRL:
- tmp_read_data = core_ctrl;
- ADDR_STATUS:
- tmp_read_data = core_status;
+ tmp_read_data = 32'h00000000;
+
+ if (cs && !we)
+ begin
+ // read operations
+ if ((address >= ADDR_BLOCK) &&
+ (address < ADDR_BLOCK + BLOCK_WORDS))
+ tmp_read_data = block_reg[((address - ADDR_BLOCK) * 32)+:32];
+ else if ((address >= ADDR_DIGEST) &&
+ (address < ADDR_DIGEST + DIGEST_WORDS))
+ tmp_read_data = digest_reg[((address - ADDR_DIGEST) * 32)+:32];
+ else
+ case (address)
+ ADDR_NAME0:
+ tmp_read_data = core_name0;
+ ADDR_NAME1:
+ tmp_read_data = core_name1;
+ ADDR_VERSION:
+ tmp_read_data = core_version;
+ ADDR_CTRL:
+ tmp_read_data = core_ctrl;
+ ADDR_STATUS:
+ tmp_read_data = core_status;
ADDR_WORK_FACTOR_NUM:
tmp_read_data = work_factor_num_reg;
- endcase
- end
+ endcase
+ end
end
always @(posedge clk)
begin
- tmp_read_data_reg <= tmp_read_data;
+ tmp_read_data_reg <= tmp_read_data;
end
endmodule // sha512
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 16:54:29 +0000