path: root/rtl/src/verilog/eim_indicator.v

`timescale 1ns / 1ps

module eim_indicator
	(
		sys_clk, sys_rst,
		eim_active,
		led_out
    );
	 
		//
		// Ports
		//
	input		wire	sys_clk;
	input		wire	sys_rst;
	input		wire	eim_active;
	output	wire	led_out;

		//
		// Parameters
		//
	localparam	CNT_BITS		= 24;	// led will be dim for 2**(24-1) = 8388608 ticks, which is ~100 ms @ 80 MHz.

		//
		// Counter
		//
	reg	[CNT_BITS-1:0]		cnt;
	
	always @(posedge sys_clk)
		//
		if (sys_rst)								cnt	<= {CNT_BITS{1'b0}};
		else if (cnt > {CNT_BITS{1'b0}})		cnt	<= cnt - 1'b1;
		else if (eim_active)						cnt	<= {CNT_BITS{1'b1}};

	assign led_out = ~cnt[CNT_BITS-1];
	
endmodule