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Novena base

This repo contains the Novena baseline developed as part of the Cryptech project. The design contains a new FPGA top level, now clock implemetation and reworked EIM interface.

Internally the baseline contains an arbiter to connect cores with a 32-bit memory like interface to the EIM. Finally there is SW to configure the EIM interface as well as talking to a test core in the FPGA.

For information about the EIM clocking and the baseline HW and SW design, see the documentation.

The baseline has been written by Pavel Shatov.