From cae74e11630fd2141b83f5b54184ba06a05a1918 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Wed, 12 Aug 2015 13:59:09 +0200 Subject: Changing type of README to md in order for it to be picked up by the wiki builder. --- README.md | 20 ++++++++++++++++++++ README.txt | 20 -------------------- 2 files changed, 20 insertions(+), 20 deletions(-) create mode 100644 README.md delete mode 100644 README.txt diff --git a/README.md b/README.md new file mode 100644 index 0000000..50efc6d --- /dev/null +++ b/README.md @@ -0,0 +1,20 @@ + +External Avalanche Entropy +-------------------------- +This is a test project of an entropy provider that collects entropy from +an avalanche noise based source. + +The design expects a one bit digital input noise signal. The collector +observes positive flank events in the input noise signal and measures the +time between these events using a counter. The counter is free running +and increases once for each clock cycle (currently running av 50 MHz). + +The LSB of the counter is added to a 32-bit entropy register at each +event. + +As debug output the entropy register is sampled at a given rate +(currently a few times per second). The debug output is connected to LED +on the FPGA development board. + +The project also contains project files, pin assignments and clock +definition neded to implement the design on a TerasIC DE0-Nano board. diff --git a/README.txt b/README.txt deleted file mode 100644 index 50efc6d..0000000 --- a/README.txt +++ /dev/null @@ -1,20 +0,0 @@ - -External Avalanche Entropy --------------------------- -This is a test project of an entropy provider that collects entropy from -an avalanche noise based source. - -The design expects a one bit digital input noise signal. The collector -observes positive flank events in the input noise signal and measures the -time between these events using a counter. The counter is free running -and increases once for each clock cycle (currently running av 50 MHz). - -The LSB of the counter is added to a 32-bit entropy register at each -event. - -As debug output the entropy register is sampled at a given rate -(currently a few times per second). The debug output is connected to LED -on the FPGA development board. - -The project also contains project files, pin assignments and clock -definition neded to implement the design on a TerasIC DE0-Nano board. -- cgit v1.2.3