| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-03-13 | Adding a prebuilt FPGA configuration file for the TerasIC C5G board. | Joachim Strömbergson |
| 2014-03-13 | Adding Makefile for building and running simulations. | Joachim Strömbergson |
| 2014-03-13 | Adding testbench for the coretest_test_core subsystem. | Joachim Strömbergson |
| 2014-03-13 | Adding the RTL that builds the subsystem. | Joachim Strömbergson |
| 2014-03-13 | Adding symbolic name and comment to highlight the serial port device. | Joachim Strömbergson |
| 2014-03-13 | Adding sw to run tests on a FPGA device connected to the FPGA board via a ser... | Joachim Strömbergson |
| 2014-03-13 | Adding license and readme file for the coretest_test_core subsystem. | Joachim Strömbergson |
 |
index : test/coretest_test_core | |
| Coretest module combined with the test_core as a test module | git repositories |
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