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| -rw-r--r-- | LICENSE | 23 | ||||
| -rw-r--r-- | README.md | 30 | ||||
| -rw-r--r-- | toolruns/quartus/terasic_c5g/output_files/coretest_fpga_entropy.sof | bin | 0 -> 3994008 bytes |
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@@ -0,0 +1,23 @@ +Copyright (c) 2014, Joachim Strömbergson +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\ No newline at end of file diff --git a/README.md b/README.md new file mode 100644 index 0000000..a3d9024 --- /dev/null +++ b/README.md @@ -0,0 +1,30 @@ +coretest_fpga_entropy +===================== + +Coretest system for testing FPGA based entropy source. + +## Introduction ## +This project is a coretest system dedicated to test entropy sources +within a FPGA device. The specific entropy source is based on a digital +oscillator design by Bernd Paysan. In this entropy source, we use six +instances with different frequencies. The oscillator outputs are +combined to generate a bit value. 32 bit values are combined to create a +random word. + +The system uses the coretest module to read and write 32-bit data to +core, In this case it allows a caller to read generated random 16-bit +values from the entropy source. The 16 bit data is in the LSB of the +word. + +The completc system contains a UART core for external access. The +project contains pin assignments etc to implement the system on a +TerasIC C5G board. + +## Implementation details. ## +This FPGA system consists of the following components: + +- The FPGA entropy source core +- The UART core +- The coretest core + +There are pin assignments and clock defines for the TerasIC C5G board. diff --git a/toolruns/quartus/terasic_c5g/output_files/coretest_fpga_entropy.sof b/toolruns/quartus/terasic_c5g/output_files/coretest_fpga_entropy.sof Binary files differnew file mode 100644 index 0000000..97e79ba --- /dev/null +++ b/toolruns/quartus/terasic_c5g/output_files/coretest_fpga_entropy.sof |