1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
|
//======================================================================
//
// entropy.v
// ---------
// digital HW based entropy generator.
//
//
// Author: Bernd Paysan, Joachim Strombergson
// Copyright (c) 2014, Bernd Paysan, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module entropy(input wire clk,
input wire nreset,
input wire cs,
input wire we,
input wire [7:0] addr,
input wire [15:0] dwrite,
output wire [15:0] dread,
output wire [7 : 0] debug
);
//----------------------------------------------------------------
// Symbolic names.
//----------------------------------------------------------------
// Delay in cycles between sampling random values
// and updating the debug port.
// Corresponds to about 1/10s with clock @ 50 MHz.
parameter DELAY_MAX = 32'h004c4b40;
parameter ADDR_ENT_WR_RNG1 = 8'h00;
parameter ADDR_ENT_WR_RNG2 = 8'h01;
parameter ADDR_ENT_RD_RNG1_RNG2 = 8'h10;
parameter ADDR_ENT_RD_P = 8'h11;
parameter ADDR_ENT_RD_N = 8'h12;
//----------------------------------------------------------------
// Registers.
//----------------------------------------------------------------
reg [7:0] rng1, rng2; // must be inverse to each other
reg [31 : 0] delay_ctr_reg;
reg [31 : 0] delay_ctr_new;
reg [7 : 0] debug_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [15:0] p, n;
reg [15 : 0] tmp_dread;
//----------------------------------------------------------------
// Module instantiations.
//----------------------------------------------------------------
genvar i;
generate
for(i=0; i<16; i=i+1) begin: tworoscs
rosc px(clk, nreset, rng1, rng2, p[i]);
rosc nx(clk, nreset, rng1, rng2, n[i]);
end
endgenerate
//----------------------------------------------------------------
// Concurrent assignments to connect output ports.
//----------------------------------------------------------------
assign dread = tmp_dread;
assign debug = debug_reg;
//----------------------------------------------------------------
// reg updates
//----------------------------------------------------------------
always @(posedge clk or negedge nreset)
begin
if(!nreset)
begin
rng1 <= 8'h55;
rng2 <= 8'haa;
delay_ctr_reg <= 32'h00000000;
debug_reg <= 8'h00;
end
else
begin
delay_ctr_reg <= delay_ctr_new;
if (delay_ctr_reg == 32'h00000000)
begin
debug_reg <= n[7 : 0];
end
if(cs & we) begin
case(addr)
ADDR_ENT_WR_RNG1: rng1 <= dwrite[15:8];
ADDR_ENT_WR_RNG2: rng2 <= dwrite[7:0];
default:;
endcase
end
end // else: !if(!nreset)
end
//----------------------------------------------------------------
// read_data
//----------------------------------------------------------------
always @*
begin : read_data
tmp_dread = 16'h0000;
if(cs & ~we)
case(addr)
ADDR_ENT_RD_RNG1_RNG2: tmp_dread = {rng1, rng2};
ADDR_ENT_RD_P: tmp_dread = p;
ADDR_ENT_RD_N: tmp_dread = n;
default:;
endcase
end
//----------------------------------------------------------------
// delay_ctr
//
// Simple counter that counts to DELAY_MAC. Used to slow down
// the debug port updates to human speeds.
//----------------------------------------------------------------
always @*
begin : delay_ctr
if (delay_ctr_reg == DELAY_MAX)
begin
delay_ctr_new = 32'h00000000;
end
else
begin
delay_ctr_new = delay_ctr_reg + 1'b1;
end
end // delay_ctr
endmodule // entropy
//======================================================================
// EOF entropy.v
//======================================================================
|
