From a3d42dc2b51b911c05d6b9a7cf473721329324d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Thu, 12 Jun 2014 08:54:53 +0200 Subject: Fixed spelling error. --- .../quartus/TerasIC_C5G/coretest_bp_entropy.qsf | 93 ---------------------- .../quartus/TerasIC_C5G/coretest_bp_entropy.sdc | 39 --------- 2 files changed, 132 deletions(-) delete mode 100644 tooruns/quartus/TerasIC_C5G/coretest_bp_entropy.qsf delete mode 100644 tooruns/quartus/TerasIC_C5G/coretest_bp_entropy.sdc (limited to 'tooruns') diff --git a/tooruns/quartus/TerasIC_C5G/coretest_bp_entropy.qsf b/tooruns/quartus/TerasIC_C5G/coretest_bp_entropy.qsf deleted file mode 100644 index 8573624..0000000 --- a/tooruns/quartus/TerasIC_C5G/coretest_bp_entropy.qsf +++ /dev/null @@ -1,93 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition -# Date created = 21:07:49 May 18, 2014 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# coretest_bp_entropy_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - -# General: - -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CGXFC5C6F27C7 -set_global_assignment -name TOP_LEVEL_ENTITY coretest_bp_entropy -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:07:49 MAY 18, 2014" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/modelsim -section_id eda_simulation -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - -# Pin assignments for the TerasIC C5G board: -set_location_assignment PIN_R20 -to clk -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk -set_location_assignment PIN_P11 -to reset_n -set_instance_assignment -name IO_STANDARD "1.2 V" -to reset_n -set_location_assignment PIN_M9 -to rxd -set_instance_assignment -name IO_STANDARD "2.5 V" -to rxd -set_location_assignment PIN_L9 -to txd -set_instance_assignment -name IO_STANDARD "2.5 V" -to txd -set_location_assignment PIN_L7 -to debug[0] -set_location_assignment PIN_K6 -to debug[1] -set_location_assignment PIN_D8 -to debug[2] -set_location_assignment PIN_E9 -to debug[3] -set_location_assignment PIN_A5 -to debug[4] -set_location_assignment PIN_B6 -to debug[5] -set_location_assignment PIN_H8 -to debug[6] -set_location_assignment PIN_H9 -to debug[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[0] - -# Source files: -set_global_assignment -name VERILOG_FILE //psf/Home/Sandbox/proj/cores/uart/src/rtl/uart_core.v -set_global_assignment -name VERILOG_FILE //psf/Home/Sandbox/proj/cores/uart/src/rtl/uart.v -set_global_assignment -name VERILOG_FILE //psf/Home/Sandbox/proj/cores/coretest/src/rtl/coretest.v -set_global_assignment -name VERILOG_FILE //psf/Home/Sandbox/proj/cores/coretest_bpaysan_entropy/src/rtl/rosc.v -set_global_assignment -name VERILOG_FILE //psf/Home/Sandbox/proj/cores/coretest_bpaysan_entropy/src/rtl/entropy.v -set_global_assignment -name VERILOG_FILE //psf/Home/Sandbox/proj/cores/coretest_bpaysan_entropy/src/rtl/coretest_bp_entropy.v - -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/tooruns/quartus/TerasIC_C5G/coretest_bp_entropy.sdc b/tooruns/quartus/TerasIC_C5G/coretest_bp_entropy.sdc deleted file mode 100644 index af0b792..0000000 --- a/tooruns/quartus/TerasIC_C5G/coretest_bp_entropy.sdc +++ /dev/null @@ -1,39 +0,0 @@ -#************************************************************ -# THIS IS A WIZARD-GENERATED FILE. -# -# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition -# -#************************************************************ - -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - - - -# Clock constraints - -create_clock -name "clk" -period 20.000ns [get_ports {clk}] -waveform {0.000 10.000} - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -- cgit v1.2.3