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Diffstat (limited to 'src/rtl/rosc.v')
-rw-r--r-- | src/rtl/rosc.v | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/src/rtl/rosc.v b/src/rtl/rosc.v new file mode 100644 index 0000000..9494261 --- /dev/null +++ b/src/rtl/rosc.v @@ -0,0 +1,60 @@ +//====================================================================== +// +// rosc.v +// --------- +// Digital ring oscillator used as entropy source. +// +// +// Author: Bernd Paysan +// Copyright (c) 2014, Bernd Paysan +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or +// without modification, are permitted provided that the following +// conditions are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module rosc(clk, nreset, in1, in2, dout); + parameter l=8; + input clk, nreset; + input [l-1:0] in1, in2; + output reg dout; + + wire cin; + wire [l:0] sum = in1 + in2 + cin; + + assign cin = ~sum[l]; + + always @(posedge clk or negedge nreset) + if(!nreset) + dout <= 0; + else + dout <= sum[l]; + +endmodule // rosc + +//====================================================================== +// EOF rosc.v +//====================================================================== |