/* * stm-sdram.c * ----------- * Functions concerning the 2x512 Mbit SDRAM working memory. * * Copyright (c) 2016, NORDUnet A/S All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * - Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * - Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * - Neither the name of the NORDUnet nor the names of its contributors may * be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "stm32f4xx_hal.h" #include "stm-init.h" #include "stm-sdram.h" #include "stm-fmc.h" #include "stm-led.h" /* Mode Register Bits */ #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) SDRAM_HandleTypeDef hsdram1; SDRAM_HandleTypeDef hsdram2; static void _sdram_init_gpio(void); static HAL_StatusTypeDef _sdram_init_fmc(void); static HAL_StatusTypeDef _sdram_init_params(SDRAM_HandleTypeDef *sdram1, SDRAM_HandleTypeDef *sdram2); HAL_StatusTypeDef sdram_init(void) { HAL_StatusTypeDef status; static int initialized = 0; if (initialized) { return HAL_OK; } initialized = 1; /* We rely on several things being set up by fmc_init() instead of duplicating all * that code here for independent FPGA/SDRAM FMC setup. This means the FPGA<->STM32 * FMC bus can be used without the SDRAMs initialized, but the SDRAMs can't be * initialized withouth the FPGA<->STM32 FMC bus being set up too. */ fmc_init(); // configure FMC _sdram_init_gpio(); status = _sdram_init_fmc(); if (status != HAL_OK) return status; // configure SDRAM registers status = _sdram_init_params(&hsdram1, &hsdram2); if (status != HAL_OK) return status; return HAL_OK; } static void _sdram_init_gpio(void) { GPIO_InitTypeDef GPIO_InitStruct; /* The bulk of the FMC GPIO pins are set up in fmc_init_gpio(). * This function just needs to enable the additional ones used * with the SDRAMs. */ fmc_af_gpio(GPIOB, GPIO_PIN_5 | GPIO_PIN_6); fmc_af_gpio(GPIOC, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3); fmc_af_gpio(GPIOE, GPIO_PIN_0 | GPIO_PIN_1); fmc_af_gpio(GPIOF, GPIO_PIN_11); fmc_af_gpio(GPIOG, GPIO_PIN_8 | GPIO_PIN_15); fmc_af_gpio(GPIOI, GPIO_PIN_4 | GPIO_PIN_5); } static HAL_StatusTypeDef _sdram_init_fmc() { HAL_StatusTypeDef status; FMC_SDRAM_TimingTypeDef SdramTiming; /* * following settings are for -75E speed grade memory chip * clocked at only 90 MHz instead of the rated 133 MHz * * ExitSelfRefreshDelay: 67 ns @ 90 MHz is 6.03 cycles, so in theory * 6 can be used here, but let's be on the safe side * * WriteRecoveryTime: must be >= tRAS - tRCD (5 - 2 = 3 cycles), * and >= tRC - tRCD - tRP (8 - 2 - 2 = 4 cycles) */ SdramTiming.LoadToActiveDelay = 2; // tMRD SdramTiming.ExitSelfRefreshDelay = 7; // (see above) SdramTiming.SelfRefreshTime = 5; // should be >= tRAS (5 cycles) SdramTiming.RowCycleDelay = 8; // tRC SdramTiming.WriteRecoveryTime = 4; // (see above) SdramTiming.RPDe
PROJ = hsm

# objs in addition to $(PROJ).o
OBJS = crc32.o \
	mgmt-cli.o \
	mgmt-firmware.c \
	mgmt-bootloader.c \
	mgmt-fpga.c \
	mgmt-keystore.c \
	mgmt-masterkey.c \
	mgmt-misc.c \
	mgmt-thread.c

BOARD_OBJS = \
	$(TOPLEVEL)/stm-init.o \
	$(TOPLEVEL)/stm-fmc.o \
	$(TOPLEVEL)/stm-uart.o \
	$(TOPLEVEL)/syscalls.o \
	$(TOPLEVEL)/stm-rtc.o \
	$(TOPLEVEL)/spiflash_n25q128.o \
	$(TOPLEVEL)/stm-fpgacfg.o \
	$(TOPLEVEL)/stm-keystore.o \
	$(TOPLEVEL)/stm-sdram.o \
	$(TOPLEVEL)/stm-flash.o \
	$(BOARD_DIR)/TOOLCHAIN_GCC_ARM/startup_stm32f429xx_rtos.o \
	$(BOARD_DIR)/system_stm32f4xx.o \
	$(BOARD_DIR)/stm32f4xx_hal_msp.o \
	$(BOARD_DIR)/stm32f4xx_it_rtos.o

CFLAGS += -DNUM_RPC_TASK=4

CFLAGS += -I$(LIBHAL_SRC)
CFLAGS += -I$(LIBCLI_SRC)
CFLAGS += -I$(RTOS_DIR)/rtos -I$(RTOS_DIR)/rtx/TARGET_CORTEX_M

LIBS += $(LIBHAL_BLD)/libhal.a $(LIBTFM_BLD)/libtfm.a
LIBS += $(LIBCLI_BLD)/libcli.a
LIBS += $(RTOS_DIR)/librtos.a

all: $(PROJ:=.elf)

%.elf: %.o $(BOARD_OBJS) $(OBJS) $(LIBS)
	$(CC) $(CFLAGS) $^ -o $@ -T$(LDSCRIPT) -g -Wl,-Map=$*.map
	$(OBJCOPY) -O binary $*.elf $*.bin
	$(SIZE) $*.elf

clean:
	rm -f *.o
	rm -f *.elf
	rm -f *.bin
	rm -f *.map
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